// **************************************************************
// Copyright (c) 2021 Xidian University.
// File name     : np_interface.v
// Module name   : 
// Created Date  : 2021-07-21 12:43:35
// Author        : Yangweiyi
// Email         : ywyxidian@163.com
// -------------------------------------------------------------------------
// Version       : 
// Last Modified : 2022-06-14 12:44:08
// Modified By   : Wangzekun
// -------------------------------------------------------------------------
// 
// -------------------------------------------------------------------------
// HISTORY       : v0.9
// Date         By  Comments
// ------------ --  ----------------------------------------------------------
// v0.1--add module ahb jtag mac np
// v0.2--add np dma module,and add axi_m interface
// v0.3--add another np dma module and corrsponding add axi_m interface
// v0.4--address size from 32 to 40,and change ID width
// v0.5--unite code version, ahb decode address is 21bit, include 2*bus_x2(2*bus), DMA
// v0.6--move DMA0 & DMA1 module to double bus module
// v0.7--add dma channel & sel, fix pullup/pulldown register for io_pad
// v0.8--modificate the connection of the signal of bus1_table_addr/bus1_table_ram_addr_convert/bus1_table_data
// v0.9--dma_channel_sel0/1
// 
// **************************************************************
`include "top_define.v"
module np_subsys_ahb #(
    parameter integer NP_DMA0_BASE_ADDR     = 32'h8FF0_0000,
    parameter integer NP_DMA1_BASE_ADDR     = 32'h8FF1_0000,
    parameter integer MAC_USER_WIDTH        = 4,
    parameter integer AXI_BURST_LEN         = 256,
    parameter integer AXI_ID_WIDTH          = 6,
    parameter integer AXI_ADDR_WIDTH        = 40,
    parameter integer AXI_DATA_WIDTH        = 128,
    parameter integer AXI_LIB_WIDTH         = 11, //Width of Max Transmit Length(in BYTES)
    parameter integer AXI_AWUSER_WIDTH      = 1,
    parameter integer AXI_ARUSER_WIDTH      = 1,
    parameter integer AXI_WUSER_WIDTH       = 1,
    parameter integer AXI_RUSER_WIDTH       = 1,
    parameter integer AXI_BUSER_WIDTH       = 1,
    parameter integer AXI_MAX_TRN_NUM       = 32, //Max transaction(outstanding) number
    parameter integer AXI_DATA_FIFO_DEPTH   = 512
 )
 (
  input  wire         ahbclk      ,
  input  wire         ahbresetn   ,
  input  wire         pkt_rstn    ,
  input  wire         pkt_clk     ,
  input  wire         clk_mac1    ,
  input  wire         clk_mac2    ,
    // input            arstn_mac1,
    // input            arstn_mac2, 

// JTAG interface
  input  wire         jtag_clk     ,
  //input  wire         jtag_clk_n,
  input  wire         jtag_trst    ,
  input  wire         jtag_tms     ,
  input  wire         jtag_tdi     ,
  output wire         jtag_tdo     ,
  output wire         jtag_tdo_en  ,

//ahb_cfg
  input  wire [31:0]  haddr_ahbm,
  input  wire [2:0]   hburst_ahbm,
  input  wire [3:0]   hprot_ahbm,
  input  wire [2:0]   hsize_ahbm,
  input  wire [1:0]   htrans_ahbm,
  input  wire [31:0]  hwdata_ahbm,
  input  wire         hwrite_ahbm,
  input  wire         hready_ahbm,
  output wire [31:0]  hrdata_ahbm,
  output wire         hreadyout_ahbm,
  output wire         hresp_ahbm,
  input  wire         hselx_ahbm,
//phy clk_pad no use
   inout wire   ref_pad_clk_m_0 ,
   inout wire   ref_pad_clk_p_0 ,
   inout wire   ref_pad_clk_m_1 ,
   inout wire   ref_pad_clk_p_1 ,
   inout wire   ref_pad_clk_m_2 ,
   inout wire   ref_pad_clk_p_2 ,
   inout wire   ref_pad_clk_m_3 ,
   inout wire   ref_pad_clk_p_3 ,
   
   //phy power
   inout wire   rx0_m_0 ,//in&out
   inout wire   rx0_p_0 ,
   inout wire   rx1_m_0 ,
   inout wire   rx1_p_0 ,
   inout wire   rx2_m_0 ,
   inout wire   rx2_p_0 ,
   inout wire   rx3_m_0 ,
   inout wire   rx3_p_0 ,
           
   inout wire  tx0_m_0 ,
   inout wire  tx0_p_0 ,
   inout wire  tx1_m_0 ,
   inout wire  tx1_p_0 ,
   inout wire  tx2_m_0 ,
   inout wire  tx2_p_0 ,
   inout wire  tx3_m_0 ,
   inout wire  tx3_p_0 ,
        
   inout wire   rx0_m_1 ,
   inout wire   rx0_p_1 ,
   inout wire   rx1_m_1 ,
   inout wire   rx1_p_1 ,
   inout wire   rx2_m_1 ,
   inout wire   rx2_p_1 ,
   inout wire   rx3_m_1 ,
   inout wire   rx3_p_1 ,
           
   inout wire  tx0_m_1 ,
   inout wire  tx0_p_1 ,
   inout wire  tx1_m_1 ,
   inout wire  tx1_p_1 ,
   inout wire  tx2_m_1 ,
   inout wire  tx2_p_1 ,
   inout wire  tx3_m_1 ,
   inout wire  tx3_p_1 ,
           
   inout wire   rx0_m_2 ,
   inout wire   rx0_p_2 ,
   inout wire   rx1_m_2 ,
   inout wire   rx1_p_2 ,
   inout wire   rx2_m_2 ,
   inout wire   rx2_p_2 ,
   inout wire   rx3_m_2 ,
   inout wire   rx3_p_2 ,
           
   inout wire  tx0_m_2 ,
   inout wire  tx0_p_2 ,
   inout wire  tx1_m_2 ,
   inout wire  tx1_p_2 ,
   inout wire  tx2_m_2 ,
   inout wire  tx2_p_2 ,
   inout wire  tx3_m_2 ,
   inout wire  tx3_p_2 ,
           
   inout wire   rx0_m_3 ,
   inout wire   rx0_p_3 ,
   inout wire   rx1_m_3 ,
   inout wire   rx1_p_3 ,
   inout wire   rx2_m_3 ,
   inout wire   rx2_p_3 ,
   inout wire   rx3_m_3 ,
   inout wire   rx3_p_3 ,
           
   inout wire  tx0_m_3 ,
   inout wire  tx0_p_3 ,
   inout wire  tx1_m_3 ,
   inout wire  tx1_p_3 ,
   inout wire  tx2_m_3 ,
   inout wire  tx2_p_3 ,
   inout wire  tx3_m_3 ,
   inout wire  tx3_p_3 ,
   
   //vss&vdd
   inout  wire         vp_0,    
   inout  wire         vpdig_0,
   inout  wire         vph_0,   
   inout  wire         vptx0_0,
   inout  wire         vptx1_0,
   inout  wire         vptx2_0,
   inout  wire         vptx3_0, 
   inout  wire         vsscore_0_0,
   inout  wire         vsscore_1_0,
   inout  wire         vsscore_2_0,
   inout  wire         gd_0,
   
   inout  wire         vp_1,    
   inout  wire         vpdig_1,
   inout  wire         vph_1,   
   inout  wire         vptx0_1,
   inout  wire         vptx1_1,
   inout  wire         vptx2_1,
   inout  wire         vptx3_1, 
   inout  wire         vsscore_0_1,
   inout  wire         vsscore_1_1,
   inout  wire         vsscore_2_1,
   inout  wire         gd_1,
   
   inout  wire         vp_2,    
   inout  wire         vpdig_2,
   inout  wire         vph_2,   
   inout  wire         vptx0_2,
   inout  wire         vptx1_2,
   inout  wire         vptx2_2,
   inout  wire         vptx3_2, 
   inout  wire         vsscore_0_2,
   inout  wire         vsscore_1_2,
   inout  wire         vsscore_2_2,
   inout  wire         gd_2,
   
   inout  wire         vp_3,    
   inout  wire         vpdig_3,
   inout  wire         vph_3,   
   inout  wire         vptx0_3,
   inout  wire         vptx1_3,
   inout  wire         vptx2_3,
   inout  wire         vptx3_3, 
   inout  wire         vsscore_0_3,
   inout  wire         vsscore_1_3,
   inout  wire         vsscore_2_3,
   inout  wire         gd_3,
   
`ifdef SIM
    output wire         bus0_axi_valid_o,
    output wire [255:0] bus0_axi_data_o,
    output wire         bus0_axi_last_o,
    output wire [ 31:0] bus0_axi_keep_o,
    input  wire         bus0_axi_ready_o,
    
    input  wire         bus0_axi_valid_i,
    input  wire [255:0] bus0_axi_data_i,
    input  wire         bus0_axi_last_i,
    input  wire [ 31:0] bus0_axi_keep_i,
    output wire         bus0_axi_ready_i,
    
    output wire         bus1_axi_valid_o,
    output wire [255:0] bus1_axi_data_o,
    output wire         bus1_axi_last_o,
    output wire [ 31:0] bus1_axi_keep_o,
    input  wire         bus1_axi_ready_o,
    
    input  wire         bus1_axi_valid_i,
    input  wire [255:0] bus1_axi_data_i,
    input  wire         bus1_axi_last_i,
    input  wire [ 31:0] bus1_axi_keep_i,
    output wire         bus1_axi_ready_i,
    
    output wire         bus2_axi_valid_o,
    output wire [255:0] bus2_axi_data_o,
    output wire         bus2_axi_last_o,
    output wire [ 31:0] bus2_axi_keep_o,
    input  wire         bus2_axi_ready_o,
    
    input  wire         bus2_axi_valid_i,
    input  wire [255:0] bus2_axi_data_i,
    input  wire         bus2_axi_last_i,
    input  wire [ 31:0] bus2_axi_keep_i,
    output wire         bus2_axi_ready_i,
    
    output wire         bus3_axi_valid_o,
    output wire [255:0] bus3_axi_data_o,
    output wire         bus3_axi_last_o,
    output wire [ 31:0] bus3_axi_keep_o,
    input  wire         bus3_axi_ready_o,
    
    input  wire         bus3_axi_valid_i,
    input  wire [255:0] bus3_axi_data_i,
    input  wire         bus3_axi_last_i,
    input  wire [ 31:0] bus3_axi_keep_i,
    output wire         bus3_axi_ready_i,
`endif
   
//phy pulldown res
   inout wire resref_0,
   inout wire resref_1,
   inout wire resref_2,
   inout wire resref_3,
   
   `ifdef CPU
        output   CPU_SRAM_wren,
        output   CPU_SRAM_rden,
        output   [31:0]CPU_SRAM_wdata,
        output   [15:0]CPU_SRAM_addr,
        input    [31:0]CPU_SRAM_rdata,
        input          CPU_SRAM_rdata_vld,

        output reg [31:0]cpu_rstn_register  ,
        output reg [5:0] cpu_rxd_register   ,
        output reg [1:0] cpu_gpi_register   ,
        output reg [13:0]cpu_spi_register   ,
        output reg [10:0]cpu_fuse_register  ,
        output reg [95:0]cpu_if_data_adc_d_i_register   ,
   `endif
   // output reg [ 9:0]io_pullup_cfg_register,
   // output reg [ 9:0]io_pulldown_cfg_register,

//AXI_master interface
  input  wire                           m_axi_aclk_i,
  input  wire                           m_axi_aresetn_i,

//AXI_master interface M0
  output wire [AXI_ID_WIDTH-1 : 0]      m_axi_m0_awid_o,
  output wire [AXI_ADDR_WIDTH-1 : 0]    m_axi_m0_awaddr_o,
  output wire [7 : 0]                   m_axi_m0_awlen_o,
  output wire [2 : 0]                   m_axi_m0_awsize_o,
  output wire [1 : 0]                   m_axi_m0_awburst_o,
  output wire                           m_axi_m0_awlock_o,
  output wire [3 : 0]                   m_axi_m0_awcache_o,
  output wire [2 : 0]                   m_axi_m0_awprot_o,
  output wire [3 : 0]                   m_axi_m0_awqos_o,
  output wire [AXI_AWUSER_WIDTH-1 : 0]  m_axi_m0_awuser_o,
  output wire                           m_axi_m0_awvalid_o,
  input  wire                           m_axi_m0_awready_i,
  output wire [AXI_DATA_WIDTH-1 : 0]    m_axi_m0_wdata_o,
  output wire [AXI_DATA_WIDTH/8-1 : 0]  m_axi_m0_wstrb_o,
  output wire                           m_axi_m0_wlast_o,
  output wire [AXI_WUSER_WIDTH-1 : 0]   m_axi_m0_wuser_o,
  output wire                           m_axi_m0_wvalid_o,
  input  wire                           m_axi_m0_wready_i,
  input  wire  [AXI_ID_WIDTH-1 : 0]     m_axi_m0_bid_i,
  input  wire  [1 : 0]                  m_axi_m0_bresp_i,
  input  wire  [AXI_BUSER_WIDTH-1 : 0]  m_axi_m0_buser_i,
  input  wire                           m_axi_m0_bvalid_i,
  output wire                           m_axi_m0_bready_o,
  output wire [AXI_ID_WIDTH-1 : 0]      m_axi_m0_arid_o,
  output wire [AXI_ADDR_WIDTH-1 : 0]    m_axi_m0_araddr_o,
  output wire [7 : 0]                   m_axi_m0_arlen_o,
  output wire [2 : 0]                   m_axi_m0_arsize_o,
  output wire [1 : 0]                   m_axi_m0_arburst_o,
  output wire                           m_axi_m0_arlock_o,
  output wire [3 : 0]                   m_axi_m0_arcache_o,
  output wire [2 : 0]                   m_axi_m0_arprot_o,
  output wire [3 : 0]                   m_axi_m0_arqos_o,
  output wire [AXI_ARUSER_WIDTH-1 : 0]  m_axi_m0_aruser_o,
  output wire                           m_axi_m0_arvalid_o,
  input  wire                           m_axi_m0_arready_i,
  input  wire  [AXI_ID_WIDTH-1 : 0]     m_axi_m0_rid_i,
  input  wire  [AXI_DATA_WIDTH-1 : 0]   m_axi_m0_rdata_i,
  input  wire  [1 : 0]                  m_axi_m0_rresp_i,
  input  wire                           m_axi_m0_rlast_i,
  input  wire  [AXI_RUSER_WIDTH-1 : 0]  m_axi_m0_ruser_i,
  input  wire                           m_axi_m0_rvalid_i,
  output wire                           m_axi_m0_rready_o,
  output wire                           np_dma_m0_irq_o,

//AXI_master interface M1
  output wire [AXI_ID_WIDTH-1 : 0]      m_axi_m1_awid_o,
  output wire [AXI_ADDR_WIDTH-1 : 0]    m_axi_m1_awaddr_o,
  output wire [7 : 0]                   m_axi_m1_awlen_o,
  output wire [2 : 0]                   m_axi_m1_awsize_o,
  output wire [1 : 0]                   m_axi_m1_awburst_o,
  output wire                           m_axi_m1_awlock_o,
  output wire [3 : 0]                   m_axi_m1_awcache_o,
  output wire [2 : 0]                   m_axi_m1_awprot_o,
  output wire [3 : 0]                   m_axi_m1_awqos_o,
  output wire [AXI_AWUSER_WIDTH-1 : 0]  m_axi_m1_awuser_o,
  output wire                           m_axi_m1_awvalid_o,
  input  wire                           m_axi_m1_awready_i,
  output wire [AXI_DATA_WIDTH-1 : 0]    m_axi_m1_wdata_o,
  output wire [AXI_DATA_WIDTH/8-1 : 0]  m_axi_m1_wstrb_o,
  output wire                           m_axi_m1_wlast_o,
  output wire [AXI_WUSER_WIDTH-1 : 0]   m_axi_m1_wuser_o,
  output wire                           m_axi_m1_wvalid_o,
  input  wire                           m_axi_m1_wready_i,
  input  wire  [AXI_ID_WIDTH-1 : 0]     m_axi_m1_bid_i,
  input  wire  [1 : 0]                  m_axi_m1_bresp_i,
  input  wire  [AXI_BUSER_WIDTH-1 : 0]  m_axi_m1_buser_i,
  input  wire                           m_axi_m1_bvalid_i,
  output wire                           m_axi_m1_bready_o,
  output wire [AXI_ID_WIDTH-1 : 0]      m_axi_m1_arid_o,
  output wire [AXI_ADDR_WIDTH-1 : 0]    m_axi_m1_araddr_o,
  output wire [7 : 0]                   m_axi_m1_arlen_o,
  output wire [2 : 0]                   m_axi_m1_arsize_o,
  output wire [1 : 0]                   m_axi_m1_arburst_o,
  output wire                           m_axi_m1_arlock_o,
  output wire [3 : 0]                   m_axi_m1_arcache_o,
  output wire [2 : 0]                   m_axi_m1_arprot_o,
  output wire [3 : 0]                   m_axi_m1_arqos_o,
  output wire [AXI_ARUSER_WIDTH-1 : 0]  m_axi_m1_aruser_o,
  output wire                           m_axi_m1_arvalid_o,
  input  wire                           m_axi_m1_arready_i,
  input  wire  [AXI_ID_WIDTH-1 : 0]     m_axi_m1_rid_i,
  input  wire  [AXI_DATA_WIDTH-1 : 0]   m_axi_m1_rdata_i,
  input  wire  [1 : 0]                  m_axi_m1_rresp_i,
  input  wire                           m_axi_m1_rlast_i,
  input  wire  [AXI_RUSER_WIDTH-1 : 0]  m_axi_m1_ruser_i,
  input  wire                           m_axi_m1_rvalid_i,
  output wire                           m_axi_m1_rready_o,
  output wire                           np_dma_m1_irq_o ,

//********************************************************************
// DMA config 20220709, xym
  input  wire        np_hselx_ahbm_0  ,
  input  wire        np_hready_ahbm_0 ,
  input  wire [1:0]  np_htrans_ahbm_0 ,
  input  wire [2:0]  np_hsize_ahbm_0  ,
  input  wire        np_hwrite_ahbm_0 ,
  input  wire [31:0] np_haddr_ahbm_0  ,
  input  wire [31:0] np_hwdata_ahbm_0 ,
  output wire        hreadyout_ahbm_0 ,
  output wire        hresp_ahbm_0     ,
  output wire [31:0] hrdata_np_dma_0  ,

  input  wire        np_hselx_ahbm_1  ,
  input  wire        np_hready_ahbm_1 ,
  input  wire [1:0]  np_htrans_ahbm_1 ,
  input  wire [2:0]  np_hsize_ahbm_1  ,
  input  wire        np_hwrite_ahbm_1 ,
  input  wire [31:0] np_haddr_ahbm_1  ,
  input  wire [31:0] np_hwdata_ahbm_1 ,
  output wire        hreadyout_ahbm_1 ,
  output wire        hresp_ahbm_1     ,
  output wire [31:0] hrdata_np_dma_1  ,
//********************************************************************
// UDP config channel signal
  // clock in
  input  wire                           clk_100M                    , // UDP deal main clock
  input  wire                           clk_125M                    , // be used to send RGMII_txd data
  input  wire                           clk_125M_90phase            , // 90-phase delay from "clk_125M"
  input  wire                           dcm_locked                  , // PLL locked flag
  // PHY interface
  output wire                           phyrst_n                    , // PHY chip reset
  // RGMII receive channel
  input  wire                           rgmii_rx_clk                ,
  input  wire                           rgmii_rx_ctrl               ,
  input  wire [3:0]                     rgmii_rxd                   ,
  // RGMII send channel
  output wire                           rgmii_tx_clk                ,
  output wire                           rgmii_tx_ctrl               ,
  output wire [3:0]                     rgmii_txd                   ,

  input  wire                           external_ahb_select         , // mask the UDP channel
//********************************************************************
// DFT port
  input  wire                          testmode     ,
  input  wire                          se           ,
  input  wire                          phy_scan_clk ,
  input  wire                          mbist_test   ,
  input  wire                          scan_mode    ,
  input  wire                          scan_set_rst 
);

wire [16:0]    bus1_phy_ctrl_register             ;
wire [25:0]    bus1_reset_register                ;
wire [ 8:0]    bus1_req_lb_register               ;
wire [ 8:0]    bus1_ack_register_temp             ;
wire [11:0]    bus1_mac_pcs_status_register1      ;
wire [27:0]    bus1_mac_pcs_status_register0_temp ;
wire [16:0]    bus1_mac_pcs_status_register2_temp ;

wire [16:0]    bus2_phy_ctrl_register             ;
wire [25:0]    bus2_reset_register                ;
wire [ 8:0]    bus2_req_lb_register               ;
wire [ 8:0]    bus2_ack_register_temp             ;
wire [11:0]    bus2_mac_pcs_status_register1      ;
wire [27:0]    bus2_mac_pcs_status_register0_temp ;
wire [16:0]    bus2_mac_pcs_status_register2_temp ;

wire [16:0]    bus3_phy_ctrl_register             ;
wire [25:0]    bus3_reset_register                ;
wire [ 8:0]    bus3_req_lb_register               ;
wire [ 8:0]    bus3_ack_register_temp             ;
wire [11:0]    bus3_mac_pcs_status_register1      ;
wire [27:0]    bus3_mac_pcs_status_register0_temp ;
wire [16:0]    bus3_mac_pcs_status_register2_temp ;

wire [16:0]    bus4_phy_ctrl_register             ;
wire [25:0]    bus4_reset_register                ;
wire [ 8:0]    bus4_req_lb_register               ;
wire [ 8:0]    bus4_ack_register_temp             ;
wire [11:0]    bus4_mac_pcs_status_register1      ;
wire [27:0]    bus4_mac_pcs_status_register0_temp ;
wire [16:0]    bus4_mac_pcs_status_register2_temp ;

wire    phy_jtag_tdo_0    ;
wire    phy_jtag_tdo_en_0 ;
wire    phy_jtag_tdo_1    ;
wire    phy_jtag_tdo_en_1 ;
wire    phy_jtag_tdo_2    ;
wire    phy_jtag_tdo_en_2 ;
wire    phy_jtag_tdo_3    ;
wire    phy_jtag_tdo_en_3 ;
wire   phy_jtag_tdi_0     ;
wire   phy_jtag_tdi_1     ;
wire   phy_jtag_tdi_2     ;
wire   phy_jtag_tdi_3     ;

wire           bus1_xpcs_reg_wren      ;
wire           bus1_xpcs_reg_rden      ;
wire [15:0]    bus1_xpcs_reg_addr      ;
wire [15:0]    bus1_xpcs_reg_din       ;
wire [15:0]    bus1_xpcs_reg_dout      ;
wire           bus1_xpcs_reg_busy      ;
wire           bus2_xpcs_reg_wren      ;
wire           bus2_xpcs_reg_rden      ;
wire [15:0]    bus2_xpcs_reg_addr      ;
wire [15:0]    bus2_xpcs_reg_din       ;
wire [15:0]    bus2_xpcs_reg_dout      ;
wire           bus2_xpcs_reg_busy      ;
wire           bus3_xpcs_reg_wren      ;
wire           bus3_xpcs_reg_rden      ;
wire [15:0]    bus3_xpcs_reg_addr      ;
wire [15:0]    bus3_xpcs_reg_din       ;
wire [15:0]    bus3_xpcs_reg_dout      ;
wire           bus3_xpcs_reg_busy      ;
wire           bus4_xpcs_reg_wren      ;
wire           bus4_xpcs_reg_rden      ;
wire [15:0]    bus4_xpcs_reg_addr      ;
wire [15:0]    bus4_xpcs_reg_din       ;
wire [15:0]    bus4_xpcs_reg_dout      ;
wire           bus4_xpcs_reg_busy      ;
wire           bus1_xlpcs_reg_wren     ;
wire           bus1_xlpcs_reg_rden     ;
wire [15:0]    bus1_xlpcs_reg_addr     ;
wire [15:0]    bus1_xlpcs_reg_din      ;
wire [15:0]    bus1_xlpcs_reg_dout     ;
wire           bus1_xlpcs_reg_busy     ;
wire           bus2_xlpcs_reg_wren     ;
wire           bus2_xlpcs_reg_rden     ;
wire [15:0]    bus2_xlpcs_reg_addr     ;
wire [15:0]    bus2_xlpcs_reg_din      ;
wire [15:0]    bus2_xlpcs_reg_dout     ;
wire           bus2_xlpcs_reg_busy     ;
wire           bus3_xlpcs_reg_wren     ;
wire           bus3_xlpcs_reg_rden     ;
wire [15:0]    bus3_xlpcs_reg_addr     ;
wire [15:0]    bus3_xlpcs_reg_din      ;
wire [15:0]    bus3_xlpcs_reg_dout     ;
wire           bus3_xlpcs_reg_busy     ;
wire           bus4_xlpcs_reg_wren     ;
wire           bus4_xlpcs_reg_rden     ;
wire [15:0]    bus4_xlpcs_reg_addr     ;
wire [15:0]    bus4_xlpcs_reg_din      ;
wire [15:0]    bus4_xlpcs_reg_dout     ;
wire           bus4_xlpcs_reg_busy     ;
wire           bus1_mac_reg_wren       ;
wire           bus1_mac_reg_rden       ;
wire [ 7:0]    bus1_mac_reg_addr       ;
wire [31:0]    bus1_mac_reg_din        ;
wire [31:0]    bus1_mac_reg_dout       ;
wire           bus1_mac_reg_busy       ;
wire           bus2_mac_reg_wren       ;
wire           bus2_mac_reg_rden       ;
wire [ 7:0]    bus2_mac_reg_addr       ;
wire [31:0]    bus2_mac_reg_din        ;
wire [31:0]    bus2_mac_reg_dout       ;
wire           bus2_mac_reg_busy       ;
wire           bus3_mac_reg_wren       ;
wire           bus3_mac_reg_rden       ;
wire [ 7:0]    bus3_mac_reg_addr       ;
wire [31:0]    bus3_mac_reg_din        ;
wire [31:0]    bus3_mac_reg_dout       ;
wire           bus3_mac_reg_busy       ;
wire           bus4_mac_reg_wren       ;
wire           bus4_mac_reg_rden       ;
wire [ 7:0]    bus4_mac_reg_addr       ;
wire [31:0]    bus4_mac_reg_din        ;
wire [31:0]    bus4_mac_reg_dout       ;
wire           bus4_mac_reg_busy       ;
wire [63:0]    bus1_mac_tx_ts          ;
wire [63:0]    bus1_mac_frc_in_tx      ;
wire [63:0]    bus1_mac_frc_in_rx      ;
wire [63:0]    bus2_mac_tx_ts          ;
wire [63:0]    bus2_mac_frc_in_tx      ;
wire [63:0]    bus2_mac_frc_in_rx      ;
wire [63:0]    bus3_mac_tx_ts          ;
wire [63:0]    bus3_mac_frc_in_tx      ;
wire [63:0]    bus3_mac_frc_in_rx      ;
wire [63:0]    bus4_mac_tx_ts          ;
wire [63:0]    bus4_mac_frc_in_tx      ;
wire [63:0]    bus4_mac_frc_in_rx      ;

wire  fp_sch_init_done0 ;
wire  fp_sch_init_done1 ;
wire  fp_sch_init_done2 ;
wire  fp_sch_init_done3 ;

wire [31:0] npsys_data_in            ;
wire [16:0] npsys_addr_in            ;
wire [31:0] npsys_data_in_1          ;
wire [16:0] npsys_addr_in_1          ;
wire        npsys_wr_in_bus1         ;
wire        npsys_rd_in_bus1         ;
wire [31:0] bus1_npsys_data_out      ;
wire        bus1_npsys_data_out_vld  ;
wire        npsys_wr_in_bus2         ;
wire        npsys_rd_in_bus2         ;
wire [31:0] bus2_npsys_data_out      ;
wire        bus2_npsys_data_out_vld  ;
wire        npsys_wr_in_bus3         ;
wire        npsys_rd_in_bus3         ;
wire [31:0] bus3_npsys_data_out      ;
wire        bus3_npsys_data_out_vld  ;
wire        npsys_wr_in_bus4         ;
wire        npsys_rd_in_bus4         ;
wire [31:0] bus4_npsys_data_out      ;
wire        bus4_npsys_data_out_vld  ;

wire uni_tx_rdy00 ;
wire uni_tx_rdy01 ;
wire uni_tx_rdy02 ;
wire uni_tx_rdy03 ;
wire mul_tx_rdy00 ;
wire mul_tx_rdy01 ;
wire mul_tx_rdy02 ;
wire mul_tx_rdy03 ;
wire uni_tx_rdy10 ;
wire uni_tx_rdy11 ;
wire uni_tx_rdy12 ;
wire uni_tx_rdy13 ;
wire mul_tx_rdy10 ;
wire mul_tx_rdy11 ;
wire mul_tx_rdy12 ;
wire mul_tx_rdy13 ;
wire uni_tx_rdy20 ;
wire uni_tx_rdy21 ;
wire uni_tx_rdy22 ;
wire uni_tx_rdy23 ;
wire mul_tx_rdy20 ;
wire mul_tx_rdy21 ;
wire mul_tx_rdy22 ;
wire mul_tx_rdy23 ;
wire uni_tx_rdy30 ;
wire uni_tx_rdy31 ;
wire uni_tx_rdy32 ;
wire uni_tx_rdy33 ;
wire mul_tx_rdy30 ;
wire mul_tx_rdy31 ;
wire mul_tx_rdy32 ;
wire mul_tx_rdy33 ;

wire [255:0] emac_data_in0     ;
wire         emac_data_wren0   ;
wire [  5:0] rx_address_dpram0 ;
wire [  3:0] mac_dest_port_in0 ;
wire         mul_indicate0     ;
wire [255:0] emac_data_in1     ;
wire         emac_data_wren1   ;
wire [  5:0] rx_address_dpram1 ;
wire [  3:0] mac_dest_port_in1 ;
wire         mul_indicate1     ;
wire [255:0] emac_data_in2     ;
wire         emac_data_wren2   ;
wire [  5:0] rx_address_dpram2 ;
wire [  3:0] mac_dest_port_in2 ;
wire         mul_indicate2     ;
wire [255:0] emac_data_in3     ;
wire         emac_data_wren3   ;
wire [  5:0] rx_address_dpram3 ;
wire [  3:0] mac_dest_port_in3 ;
wire         mul_indicate3     ;

wire           pkt_sop_i_40_0  ;
wire [255:0]   pkt_data_i_40_0 ;
wire           pkt_eop_i_40_0  ;
wire [4:0]     pkt_mod_i_40_0  ;
wire           pkt_dval_i_40_0 ;
wire           pkt_sop_i_40_1  ;
wire [255:0]   pkt_data_i_40_1 ;
wire           pkt_eop_i_40_1  ;
wire [4:0]     pkt_mod_i_40_1  ;
wire           pkt_dval_i_40_1 ;
wire           pkt_sop_i_10_0  ;
wire [255:0]   pkt_data_i_10_0 ;
wire           pkt_eop_i_10_0  ;
wire [4:0]     pkt_mod_i_10_0  ;
wire           pkt_dval_i_10_0 ;
wire           pkt_sop_i_10_1  ;
wire [255:0]   pkt_data_i_10_1 ;
wire           pkt_eop_i_10_1  ;
wire [4:0]     pkt_mod_i_10_1  ;
wire           pkt_dval_i_10_1 ;

// wire [9 :0]     ram_2p_cfg_register ;
// wire [11:0]     ram_dp_cfg_register ;
// wire [6 :0]     rf_2p_cfg_register  ;

wire [9 :0] ram_2p_cfg_out_0 ;
wire [11:0] ram_dp_cfg_out_0 ;
wire [6 :0] rf_2p_cfg_out_0  ;
wire [9 :0] ram_2p_cfg_out_1 ;
wire [11:0] ram_dp_cfg_out_1 ;
wire [6 :0] rf_2p_cfg_out_1  ;

wire emac_rx_ready0 ;
wire emac_rx_ready1 ;
wire emac_rx_ready2 ;
wire emac_rx_ready3 ;

// 20220709, xym
// wire            np_hselx_ahbm  ;
// wire            np_hready_ahbm ;
// wire [1:0]      np_htrans_ahbm ;
// wire [2:0]      np_hsize_ahbm  ;
// wire            np_hwrite_ahbm ;
// wire [31:0]     np_haddr_ahbm  ;
// wire [31:0]     np_hwdata_ahbm ;

// wire [31:0] hrdata_np_dma_0 ;
// wire [31:0] hrdata_np_dma_1 ;

wire [9:0]      bus1_table_addr               ;
wire [9:0]      bus1_table_ram_addr_convert   ;
wire [71:0]     bus1_table_data               ;
wire [71:0]     bus1_table_ram_data_convert   ;
wire            bus1_table_wren               ;
wire            bus1_table_ram_wr_en_convert  ;
wire [9:0]      bus2_table_addr               ;
wire [9:0]      bus2_table_ram_addr_convert   ;
wire [71:0]     bus2_table_data               ;
wire [71:0]     bus2_table_ram_data_convert   ;
wire            bus2_table_wren               ;
wire            bus2_table_ram_wr_en_convert  ;
wire [9:0]      bus3_table_addr               ;
wire [9:0]      bus3_table_ram_addr_convert   ;
wire [71:0]     bus3_table_data               ;
wire [71:0]     bus3_table_ram_data_convert   ;
wire            bus3_table_wren               ;
wire            bus3_table_ram_wr_en_convert  ;
wire [9:0]      bus4_table_addr               ;
wire [9:0]      bus4_table_ram_addr_convert   ;
wire [71:0]     bus4_table_data               ;
wire [71:0]     bus4_table_ram_data_convert   ;
wire            bus4_table_wren               ;
wire            bus4_table_ram_wr_en_convert  ;

wire clk156_p;
assign clk156_p = clk_mac2;

wire    res_ack_in_0    ;
wire    res_ack_out_0   ;
wire    res_req_in_0    ;
wire    res_req_out_0   ;
wire    res_ack_in_1    ;
wire    res_ack_out_1   ;
wire    res_req_in_1    ;
wire    res_req_out_1   ;
wire    res_ack_in_2    ;
wire    res_ack_out_2   ;
wire    res_req_in_2    ;
wire    res_req_out_2   ;
wire    res_ack_in_3    ;
wire    res_ack_out_3   ;
wire    res_req_in_3    ;
wire    res_req_out_3   ;

wire [1:0]   dma_channel_sel0 ;
wire [1:0]   dma_channel_sel1 ;

assign res_req_in_0 = 1'b0;
assign res_req_in_1 = res_req_out_0;
assign res_req_in_2 = res_req_out_1;
assign res_req_in_3 = res_req_out_2;

assign res_ack_in_3 = res_req_out_3;
assign res_ack_in_2 = res_ack_out_3;
assign res_ack_in_1 = res_ack_out_2;
assign res_ack_in_0 = res_ack_out_1;
// #########################################################################################
//np_misc
// #########################################################################################
np_misc u_np_misc (
  .ahbclk     (ahbclk   ) ,
  .ahbresetn  (ahbresetn) ,
  .pkt_rstn   (pkt_rstn ) ,
  .pkt_clk    (pkt_clk  ) ,

  .jtag_clk    (jtag_clk   ) ,
  .jtag_trst   (jtag_trst  ) ,
  .jtag_tms    (jtag_tms   ) ,
  .jtag_tdi    (jtag_tdi   ) ,
  .jtag_tdo    (jtag_tdo   ) ,
  .jtag_tdo_en (jtag_tdo_en) ,

  .haddr_ahbm     (haddr_ahbm     ),
  .hburst_ahbm    (hburst_ahbm    ),
  .hprot_ahbm     (hprot_ahbm     ),
  .hsize_ahbm     (hsize_ahbm     ),
  .htrans_ahbm    (htrans_ahbm    ),
  .hwdata_ahbm    (hwdata_ahbm    ),
  .hwrite_ahbm    (hwrite_ahbm    ),
  .hready_ahbm    (hready_ahbm    ),
  .hrdata_ahbm    (hrdata_ahbm    ),
  .hreadyout_ahbm (hreadyout_ahbm ),
  .hresp_ahbm     (hresp_ahbm     ),
  .hselx_ahbm     (hselx_ahbm     ),

`ifdef SIM
  .bus0_axi_valid_i (bus0_axi_valid_i ),
  .bus0_axi_data_i  (bus0_axi_data_i  ),
  .bus0_axi_last_i  (bus0_axi_last_i  ),
  .bus0_axi_keep_i  (bus0_axi_keep_i  ),
  .bus0_axi_ready_i (bus0_axi_ready_i ),

  .bus1_axi_valid_i (bus1_axi_valid_i ),
  .bus1_axi_data_i  (bus1_axi_data_i  ),
  .bus1_axi_last_i  (bus1_axi_last_i  ),
  .bus1_axi_keep_i  (bus1_axi_keep_i  ),
  .bus1_axi_ready_i (bus1_axi_ready_i ),

  .bus2_axi_valid_i (bus2_axi_valid_i ),
  .bus2_axi_data_i  (bus2_axi_data_i  ),
  .bus2_axi_last_i  (bus2_axi_last_i  ),
  .bus2_axi_keep_i  (bus2_axi_keep_i  ),
  .bus2_axi_ready_i (bus2_axi_ready_i ),

  .bus3_axi_valid_i (bus3_axi_valid_i ),
  .bus3_axi_data_i  (bus3_axi_data_i  ),
  .bus3_axi_last_i  (bus3_axi_last_i  ),
  .bus3_axi_keep_i  (bus3_axi_keep_i  ),
  .bus3_axi_ready_i (bus3_axi_ready_i ),
`endif

`ifdef CPU
  .CPU_SRAM_wren      (CPU_SRAM_wren       ),
  .CPU_SRAM_rden      (CPU_SRAM_rden       ),
  .CPU_SRAM_wdata     (CPU_SRAM_wdata      ),
  .CPU_SRAM_addr      (CPU_SRAM_addr       ),
  .CPU_SRAM_rdata     (CPU_SRAM_rdata      ),
  .CPU_SRAM_rdata_vld (CPU_SRAM_rdata_vld  ),

  .cpu_rstn_register            (cpu_rstn_register             ) ,
  .cpu_rxd_register             (cpu_rxd_register              ) ,
  .cpu_gpi_register             (cpu_gpi_register              ) ,
  .cpu_spi_register             (cpu_spi_register              ) ,
  .cpu_fuse_register            (cpu_fuse_register             ) ,
  .cpu_if_data_adc_d_i_register (cpu_if_data_adc_d_i_register  ) ,
`endif

  // .io_pullup_cfg_register   (io_pullup_cfg_register  ),
  // .io_pulldown_cfg_register (io_pulldown_cfg_register),

.clk_100M            (clk_100M            ) ,
.clk_125M            (clk_125M            ) ,
.clk_125M_90phase    (clk_125M_90phase    ) ,
.dcm_locked          (dcm_locked          ) ,
.phyrst_n            (phyrst_n            ) ,
.rgmii_rx_clk        (rgmii_rx_clk        ) ,
.rgmii_rx_ctrl       (rgmii_rx_ctrl       ) ,
.rgmii_rxd           (rgmii_rxd           ) ,
.rgmii_tx_clk        (rgmii_tx_clk        ) ,
.rgmii_tx_ctrl       (rgmii_tx_ctrl       ) ,
.rgmii_txd           (rgmii_txd           ) ,
.external_ahb_select (external_ahb_select ) ,

.bus1_phy_ctrl_register              (bus1_phy_ctrl_register             ) ,
.bus1_reset_register                 (bus1_reset_register                ) ,
.bus1_req_lb_register                (bus1_req_lb_register               ) ,
.bus1_ack_register_temp              (bus1_ack_register_temp             ) ,
.bus1_mac_pcs_status_register1       (bus1_mac_pcs_status_register1      ) ,
.bus1_mac_pcs_status_register0_temp  (bus1_mac_pcs_status_register0_temp ) ,
.bus1_mac_pcs_status_register2_temp  (bus1_mac_pcs_status_register2_temp ) ,

.bus2_phy_ctrl_register              (bus2_phy_ctrl_register             ) ,
.bus2_reset_register                 (bus2_reset_register                ) ,
.bus2_req_lb_register                (bus2_req_lb_register               ) ,
.bus2_ack_register_temp              (bus2_ack_register_temp             ) ,
.bus2_mac_pcs_status_register1       (bus2_mac_pcs_status_register1      ) ,
.bus2_mac_pcs_status_register0_temp  (bus2_mac_pcs_status_register0_temp ) ,
.bus2_mac_pcs_status_register2_temp  (bus2_mac_pcs_status_register2_temp ) ,

.bus3_phy_ctrl_register              (bus3_phy_ctrl_register             ) ,
.bus3_reset_register                 (bus3_reset_register                ) ,
.bus3_req_lb_register                (bus3_req_lb_register               ) ,
.bus3_ack_register_temp              (bus3_ack_register_temp             ) ,
.bus3_mac_pcs_status_register1       (bus3_mac_pcs_status_register1      ) ,
.bus3_mac_pcs_status_register0_temp  (bus3_mac_pcs_status_register0_temp ) ,
.bus3_mac_pcs_status_register2_temp  (bus3_mac_pcs_status_register2_temp ) ,

.bus4_phy_ctrl_register              (bus4_phy_ctrl_register             ) ,
.bus4_reset_register                 (bus4_reset_register                ) ,
.bus4_req_lb_register                (bus4_req_lb_register               ) ,
.bus4_ack_register_temp              (bus4_ack_register_temp             ) ,
.bus4_mac_pcs_status_register1       (bus4_mac_pcs_status_register1      ) ,
.bus4_mac_pcs_status_register0_temp  (bus4_mac_pcs_status_register0_temp ) ,
.bus4_mac_pcs_status_register2_temp  (bus4_mac_pcs_status_register2_temp ) ,

.phy_jtag_tdo_0    (phy_jtag_tdo_0    ),
.phy_jtag_tdo_en_0 (phy_jtag_tdo_en_0 ),
.phy_jtag_tdo_1    (phy_jtag_tdo_1    ),
.phy_jtag_tdo_en_1 (phy_jtag_tdo_en_1 ),
.phy_jtag_tdo_2    (phy_jtag_tdo_2    ),
.phy_jtag_tdo_en_2 (phy_jtag_tdo_en_2 ),
.phy_jtag_tdo_3    (phy_jtag_tdo_3    ),
.phy_jtag_tdo_en_3 (phy_jtag_tdo_en_3 ),

.phy_jtag_tdi_0 (phy_jtag_tdi_0 ) ,
.phy_jtag_tdi_1 (phy_jtag_tdi_1 ) ,
.phy_jtag_tdi_2 (phy_jtag_tdi_2 ) ,
.phy_jtag_tdi_3 (phy_jtag_tdi_3 ) ,

.bus1_xpcs_reg_wren  (bus1_xpcs_reg_wren  ) ,
.bus1_xpcs_reg_rden  (bus1_xpcs_reg_rden  ) ,
.bus1_xpcs_reg_addr  (bus1_xpcs_reg_addr  ) ,
.bus1_xpcs_reg_din   (bus1_xpcs_reg_din   ) ,
.bus1_xpcs_reg_dout  (bus1_xpcs_reg_dout  ) ,
.bus1_xpcs_reg_busy  (bus1_xpcs_reg_busy  ) ,
.bus2_xpcs_reg_wren  (bus2_xpcs_reg_wren  ) ,
.bus2_xpcs_reg_rden  (bus2_xpcs_reg_rden  ) ,
.bus2_xpcs_reg_addr  (bus2_xpcs_reg_addr  ) ,
.bus2_xpcs_reg_din   (bus2_xpcs_reg_din   ) ,
.bus2_xpcs_reg_dout  (bus2_xpcs_reg_dout  ) ,
.bus2_xpcs_reg_busy  (bus2_xpcs_reg_busy  ) ,
.bus3_xpcs_reg_wren  (bus3_xpcs_reg_wren  ) ,
.bus3_xpcs_reg_rden  (bus3_xpcs_reg_rden  ) ,
.bus3_xpcs_reg_addr  (bus3_xpcs_reg_addr  ) ,
.bus3_xpcs_reg_din   (bus3_xpcs_reg_din   ) ,
.bus3_xpcs_reg_dout  (bus3_xpcs_reg_dout  ) ,
.bus3_xpcs_reg_busy  (bus3_xpcs_reg_busy  ) ,
.bus4_xpcs_reg_wren  (bus4_xpcs_reg_wren  ) ,
.bus4_xpcs_reg_rden  (bus4_xpcs_reg_rden  ) ,
.bus4_xpcs_reg_addr  (bus4_xpcs_reg_addr  ) ,
.bus4_xpcs_reg_din   (bus4_xpcs_reg_din   ) ,
.bus4_xpcs_reg_dout  (bus4_xpcs_reg_dout  ) ,
.bus4_xpcs_reg_busy  (bus4_xpcs_reg_busy  ) ,

.bus1_xlpcs_reg_wren (bus1_xlpcs_reg_wren ) ,
.bus1_xlpcs_reg_rden (bus1_xlpcs_reg_rden ) ,
.bus1_xlpcs_reg_addr (bus1_xlpcs_reg_addr ) ,
.bus1_xlpcs_reg_din  (bus1_xlpcs_reg_din  ) ,
.bus1_xlpcs_reg_dout (bus1_xlpcs_reg_dout ) ,
.bus1_xlpcs_reg_busy (bus1_xlpcs_reg_busy ) ,
.bus2_xlpcs_reg_wren (bus2_xlpcs_reg_wren ) ,
.bus2_xlpcs_reg_rden (bus2_xlpcs_reg_rden ) ,
.bus2_xlpcs_reg_addr (bus2_xlpcs_reg_addr ) ,
.bus2_xlpcs_reg_din  (bus2_xlpcs_reg_din  ) ,
.bus2_xlpcs_reg_dout (bus2_xlpcs_reg_dout ) ,
.bus2_xlpcs_reg_busy (bus2_xlpcs_reg_busy ) ,
.bus3_xlpcs_reg_wren (bus3_xlpcs_reg_wren ) ,
.bus3_xlpcs_reg_rden (bus3_xlpcs_reg_rden ) ,
.bus3_xlpcs_reg_addr (bus3_xlpcs_reg_addr ) ,
.bus3_xlpcs_reg_din  (bus3_xlpcs_reg_din  ) ,
.bus3_xlpcs_reg_dout (bus3_xlpcs_reg_dout ) ,
.bus3_xlpcs_reg_busy (bus3_xlpcs_reg_busy ) ,
.bus4_xlpcs_reg_wren (bus4_xlpcs_reg_wren ) ,
.bus4_xlpcs_reg_rden (bus4_xlpcs_reg_rden ) ,
.bus4_xlpcs_reg_addr (bus4_xlpcs_reg_addr ) ,
.bus4_xlpcs_reg_din  (bus4_xlpcs_reg_din  ) ,
.bus4_xlpcs_reg_dout (bus4_xlpcs_reg_dout ) ,
.bus4_xlpcs_reg_busy (bus4_xlpcs_reg_busy ) ,

.bus1_mac_reg_wren   (bus1_mac_reg_wren   ) ,
.bus1_mac_reg_rden   (bus1_mac_reg_rden   ) ,
.bus1_mac_reg_addr   (bus1_mac_reg_addr   ) ,
.bus1_mac_reg_din    (bus1_mac_reg_din    ) ,
.bus1_mac_reg_dout   (bus1_mac_reg_dout   ) ,
.bus1_mac_reg_busy   (bus1_mac_reg_busy   ) ,
.bus2_mac_reg_wren   (bus2_mac_reg_wren   ) ,
.bus2_mac_reg_rden   (bus2_mac_reg_rden   ) ,
.bus2_mac_reg_addr   (bus2_mac_reg_addr   ) ,
.bus2_mac_reg_din    (bus2_mac_reg_din    ) ,
.bus2_mac_reg_dout   (bus2_mac_reg_dout   ) ,
.bus2_mac_reg_busy   (bus2_mac_reg_busy   ) ,
.bus3_mac_reg_wren   (bus3_mac_reg_wren   ) ,
.bus3_mac_reg_rden   (bus3_mac_reg_rden   ) ,
.bus3_mac_reg_addr   (bus3_mac_reg_addr   ) ,
.bus3_mac_reg_din    (bus3_mac_reg_din    ) ,
.bus3_mac_reg_dout   (bus3_mac_reg_dout   ) ,
.bus3_mac_reg_busy   (bus3_mac_reg_busy   ) ,
.bus4_mac_reg_wren   (bus4_mac_reg_wren   ) ,
.bus4_mac_reg_rden   (bus4_mac_reg_rden   ) ,
.bus4_mac_reg_addr   (bus4_mac_reg_addr   ) ,
.bus4_mac_reg_din    (bus4_mac_reg_din    ) ,
.bus4_mac_reg_dout   (bus4_mac_reg_dout   ) ,
.bus4_mac_reg_busy   (bus4_mac_reg_busy   ) ,

.bus1_mac_tx_ts      (bus1_mac_tx_ts      ) ,
.bus1_mac_frc_in_tx  (bus1_mac_frc_in_tx  ) ,
.bus1_mac_frc_in_rx  (bus1_mac_frc_in_rx  ) ,
.bus2_mac_tx_ts      (bus2_mac_tx_ts      ) ,
.bus2_mac_frc_in_tx  (bus2_mac_frc_in_tx  ) ,
.bus2_mac_frc_in_rx  (bus2_mac_frc_in_rx  ) ,
.bus3_mac_tx_ts      (bus3_mac_tx_ts      ) ,
.bus3_mac_frc_in_tx  (bus3_mac_frc_in_tx  ) ,
.bus3_mac_frc_in_rx  (bus3_mac_frc_in_rx  ) ,
.bus4_mac_tx_ts      (bus4_mac_tx_ts      ) ,
.bus4_mac_frc_in_tx  (bus4_mac_frc_in_tx  ) ,
.bus4_mac_frc_in_rx  (bus4_mac_frc_in_rx  ) ,

.fp_sch_init_done0 (fp_sch_init_done0 ) ,
.fp_sch_init_done1 (fp_sch_init_done1 ) ,
.fp_sch_init_done2 (fp_sch_init_done2 ) ,
.fp_sch_init_done3 (fp_sch_init_done3 ) ,

.npsys_wr_in_bus1        (npsys_wr_in_bus1        ) ,
.npsys_rd_in_bus1        (npsys_rd_in_bus1        ) ,
.bus1_npsys_data_out     (bus1_npsys_data_out     ) ,
.bus1_npsys_data_out_vld (bus1_npsys_data_out_vld ) ,
.npsys_wr_in_bus2        (npsys_wr_in_bus2        ) ,
.npsys_rd_in_bus2        (npsys_rd_in_bus2        ) ,
.bus2_npsys_data_out     (bus2_npsys_data_out     ) ,
.bus2_npsys_data_out_vld (bus2_npsys_data_out_vld ) ,
.npsys_wr_in_bus3        (npsys_wr_in_bus3        ) ,
.npsys_rd_in_bus3        (npsys_rd_in_bus3        ) ,
.bus3_npsys_data_out     (bus3_npsys_data_out     ) ,
.bus3_npsys_data_out_vld (bus3_npsys_data_out_vld ) ,
.npsys_wr_in_bus4        (npsys_wr_in_bus4        ) ,
.npsys_rd_in_bus4        (npsys_rd_in_bus4        ) ,
.bus4_npsys_data_out     (bus4_npsys_data_out     ) ,
.bus4_npsys_data_out_vld (bus4_npsys_data_out_vld ) ,

.uni_tx_rdy00 (uni_tx_rdy00) ,
.uni_tx_rdy01 (uni_tx_rdy01) ,
.uni_tx_rdy02 (uni_tx_rdy02) ,
.uni_tx_rdy03 (uni_tx_rdy03) ,
.mul_tx_rdy00 (mul_tx_rdy00) ,
.mul_tx_rdy01 (mul_tx_rdy01) ,
.mul_tx_rdy02 (mul_tx_rdy02) ,
.mul_tx_rdy03 (mul_tx_rdy03) ,
.uni_tx_rdy10 (uni_tx_rdy10) ,
.uni_tx_rdy11 (uni_tx_rdy11) ,
.uni_tx_rdy12 (uni_tx_rdy12) ,
.uni_tx_rdy13 (uni_tx_rdy13) ,
.mul_tx_rdy10 (mul_tx_rdy10) ,
.mul_tx_rdy11 (mul_tx_rdy11) ,
.mul_tx_rdy12 (mul_tx_rdy12) ,
.mul_tx_rdy13 (mul_tx_rdy13) ,
.uni_tx_rdy20 (uni_tx_rdy20) ,
.uni_tx_rdy21 (uni_tx_rdy21) ,
.uni_tx_rdy22 (uni_tx_rdy22) ,
.uni_tx_rdy23 (uni_tx_rdy23) ,
.mul_tx_rdy20 (mul_tx_rdy20) ,
.mul_tx_rdy21 (mul_tx_rdy21) ,
.mul_tx_rdy22 (mul_tx_rdy22) ,
.mul_tx_rdy23 (mul_tx_rdy23) ,
.uni_tx_rdy30 (uni_tx_rdy30) ,
.uni_tx_rdy31 (uni_tx_rdy31) ,
.uni_tx_rdy32 (uni_tx_rdy32) ,
.uni_tx_rdy33 (uni_tx_rdy33) ,
.mul_tx_rdy30 (mul_tx_rdy30) ,
.mul_tx_rdy31 (mul_tx_rdy31) ,
.mul_tx_rdy32 (mul_tx_rdy32) ,
.mul_tx_rdy33 (mul_tx_rdy33) ,

.emac_data_in0     (emac_data_in0     ),
.emac_data_wren0   (emac_data_wren0   ),
.rx_address_dpram0 (rx_address_dpram0 ),
.mac_dest_port_in0 (mac_dest_port_in0 ),
.mul_indicate0     (mul_indicate0     ),
.emac_data_in1     (emac_data_in1     ),
.emac_data_wren1   (emac_data_wren1   ),
.rx_address_dpram1 (rx_address_dpram1 ),
.mac_dest_port_in1 (mac_dest_port_in1 ),
.mul_indicate1     (mul_indicate1     ),
.emac_data_in2     (emac_data_in2     ),
.emac_data_wren2   (emac_data_wren2   ),
.rx_address_dpram2 (rx_address_dpram2 ),
.mac_dest_port_in2 (mac_dest_port_in2 ),
.mul_indicate2     (mul_indicate2     ),
.emac_data_in3     (emac_data_in3     ),
.emac_data_wren3   (emac_data_wren3   ),
.rx_address_dpram3 (rx_address_dpram3 ),
.mac_dest_port_in3 (mac_dest_port_in3 ),
.mul_indicate3     (mul_indicate3     ),

.pkt_sop_i_40_0  (pkt_sop_i_40_0  ) ,
.pkt_data_i_40_0 (pkt_data_i_40_0 ) ,
.pkt_eop_i_40_0  (pkt_eop_i_40_0  ) ,
.pkt_mod_i_40_0  (pkt_mod_i_40_0  ) ,
.pkt_dval_i_40_0 (pkt_dval_i_40_0 ) ,
.pkt_sop_i_40_1  (pkt_sop_i_40_1  ) ,
.pkt_data_i_40_1 (pkt_data_i_40_1 ) ,
.pkt_eop_i_40_1  (pkt_eop_i_40_1  ) ,
.pkt_mod_i_40_1  (pkt_mod_i_40_1  ) ,
.pkt_dval_i_40_1 (pkt_dval_i_40_1 ) ,
.pkt_sop_i_10_0  (pkt_sop_i_10_0  ) ,
.pkt_data_i_10_0 (pkt_data_i_10_0 ) ,
.pkt_eop_i_10_0  (pkt_eop_i_10_0  ) ,
.pkt_mod_i_10_0  (pkt_mod_i_10_0  ) ,
.pkt_dval_i_10_0 (pkt_dval_i_10_0 ) ,
.pkt_sop_i_10_1  (pkt_sop_i_10_1  ) ,
.pkt_data_i_10_1 (pkt_data_i_10_1 ) ,
.pkt_eop_i_10_1  (pkt_eop_i_10_1  ) ,
.pkt_mod_i_10_1  (pkt_mod_i_10_1  ) ,
.pkt_dval_i_10_1 (pkt_dval_i_10_1 ) ,

.emac_rx_ready0 (emac_rx_ready0 ) ,
.emac_rx_ready1 (emac_rx_ready1 ) ,
.emac_rx_ready2 (emac_rx_ready2 ) ,
.emac_rx_ready3 (emac_rx_ready3 ) ,

.npsys_data_in   (npsys_data_in   ) ,
.npsys_addr_in   (npsys_addr_in   ) ,
.npsys_data_in_1 (npsys_data_in_1 ) ,
.npsys_addr_in_1 (npsys_addr_in_1 ) ,

.ram_2p_cfg_out_0 (ram_2p_cfg_out_0 ),
.ram_dp_cfg_out_0 (ram_dp_cfg_out_0 ),
.rf_2p_cfg_out_0  (rf_2p_cfg_out_0  ),
.ram_2p_cfg_out_1 (ram_2p_cfg_out_1 ),
.ram_dp_cfg_out_1 (ram_dp_cfg_out_1 ),
.rf_2p_cfg_out_1  (rf_2p_cfg_out_1  ),

// .np_hselx_ahbm  (np_hselx_ahbm  ) ,
// .np_hready_ahbm (np_hready_ahbm ) ,
// .np_htrans_ahbm (np_htrans_ahbm ) ,
// .np_hsize_ahbm  (np_hsize_ahbm  ) ,
// .np_hwrite_ahbm (np_hwrite_ahbm ) ,
// .np_haddr_ahbm  (np_haddr_ahbm  ) ,
// .np_hwdata_ahbm (np_hwdata_ahbm ) ,

// .hrdata_np_dma_0 (hrdata_np_dma_0) ,
// .hrdata_np_dma_1 (hrdata_np_dma_1) ,

.dma_channel_sel0 (dma_channel_sel0),
.dma_channel_sel1 (dma_channel_sel1),

// DFT port
.mbist_test   (mbist_test),
.scan_mode    (scan_mode),
.scan_set_rst (scan_set_rst)

);

// #########################################################################################
//bus1 & bus2
// #########################################################################################
  // double_bus #(
  //   .frame_mac_dst_bus0  (48'h1000_0000_0002   ),
  //   .frame_mac_src_bus0  (48'h1000_0000_0001   ),
  //   .frame_length_bus0   (16'h88b6             ),
  //   .CLUSTER_ID0         (2'b00),

  //   .frame_mac_dst_bus1  (48'h1000_0000_0001   ),
  //   .frame_mac_src_bus1  (48'h1000_0000_0002   ),
  //   .frame_length_bus1   (16'h88b6             ),
  //   .CLUSTER_ID1         (2'b01),

  //   .NP_DMA_BASE_ADDR         (NP_DMA0_BASE_ADDR),
  //   .MAC_USER_WIDTH           (MAC_USER_WIDTH),
  //   .AXI_BURST_LEN            (AXI_BURST_LEN),
  //   .AXI_ID_WIDTH             (AXI_ID_WIDTH),
  //   .AXI_ADDR_WIDTH           (AXI_ADDR_WIDTH),
  //   .AXI_DATA_WIDTH           (AXI_DATA_WIDTH),
  //   .AXI_LIB_WIDTH            (AXI_LIB_WIDTH),
  //   .AXI_AWUSER_WIDTH         (AXI_AWUSER_WIDTH),
  //   .AXI_ARUSER_WIDTH         (AXI_ARUSER_WIDTH),
  //   .AXI_WUSER_WIDTH          (AXI_WUSER_WIDTH),
  //   .AXI_RUSER_WIDTH          (AXI_RUSER_WIDTH),
  //   .AXI_BUSER_WIDTH          (AXI_BUSER_WIDTH)
  //   ) 
  double_bus
    u_double_bus_1_2(
    // ####################################
    //bus0
    // ####################################
    //param
    .frame_mac_dst_bus0(48'h1000_0000_0002),
    .frame_mac_src_bus0(48'h1000_0000_0001),
    .cluster_id_bus0(2'b00),
    .frame_mac_dst_bus1(48'h1000_0000_0001),
    .frame_mac_src_bus1(48'h1000_0000_0002),
    .cluster_id_bus1(2'b01),
    .dma_addr(NP_DMA0_BASE_ADDR),

    //phy signals
    .vp          (vp_0)           ,    
    .vpdig       (vpdig_0)        ,    
    .vph         (vph_0)          ,     
    .vptx0       (vptx0_0)        ,     
    .vptx1       (vptx1_0)        ,     
    .vptx2       (vptx2_0)        ,     
    .vptx3       (vptx3_0)        ,     
    .vsscore_0   (vsscore_0_0)    ,        
    .vsscore_1   (vsscore_1_0)    ,        
    .vsscore_2   (vsscore_2_0)    ,        
    .gd          (gd_0)           ,

    // phy_mac_interface
    .phy_ctrl_register                   (bus1_phy_ctrl_register                 ),
    .reset_register                      (bus1_reset_register                    ),
    .req_lb_register                     (bus1_req_lb_register                   ),
    .ack_register_temp                   (bus1_ack_register_temp                 ),
    .mac_pcs_status_register1            (bus1_mac_pcs_status_register1          ),
    .mac_pcs_status_register0_temp       (bus1_mac_pcs_status_register0_temp     ),
    .mac_pcs_status_register2_temp       (bus1_mac_pcs_status_register2_temp     ),

    //jtag signals
    .jtag_tck               (jtag_clk              ),
    .jtag_tdi               (phy_jtag_tdi_0        ),
    .jtag_tdo               (phy_jtag_tdo_0        ),
    .jtag_tdo_en            (phy_jtag_tdo_en_0     ),
    .jtag_tms               (jtag_tms              ),
    .jtag_trst_n            (~jtag_trst            ),

    //clk and clk_en
    .ref_pad_clk_m          (ref_pad_clk_m_0        ),
    .ref_pad_clk_p          (ref_pad_clk_p_0        ),
    .ref_alt_clk_m          (1'b0                   ),//156
    .ref_alt_clk_p          (clk156_p               ),

    //Resistor Tune Signals
    .resref                 (resref_0               ),

    //serial data signals
    .res_ack_in     (res_ack_in_0 ),
    .res_ack_out    (res_ack_out_0),
    .res_req_in     (res_req_in_0 ),
    .res_req_out    (res_req_out_0),

    .rx0_m      (rx0_m_0),//in&out
    .rx0_p      (rx0_p_0),
    .rx1_m      (rx1_m_0),
    .rx1_p      (rx1_p_0),
    .rx2_m      (rx2_m_0),
    .rx2_p      (rx2_p_0),
    .rx3_m      (rx3_m_0),
    .rx3_p      (rx3_p_0),

    .tx0_m      (tx0_m_0),
    .tx0_p      (tx0_p_0),
    .tx1_m      (tx1_m_0),
    .tx1_p      (tx1_p_0),
    .tx2_m      (tx2_m_0),
    .tx2_p      (tx2_p_0),
    .tx3_m      (tx3_m_0),
    .tx3_p      (tx3_p_0),

    //mac signals
    .ref_ff_clk_630plus       (clk_mac1 ),
    .reg_clk                  (pkt_clk  ),

    .xpcs_reg_wren     (bus1_xpcs_reg_wren),
    .xpcs_reg_rden     (bus1_xpcs_reg_rden),
    .xpcs_reg_addr     (bus1_xpcs_reg_addr),
    .xpcs_reg_din      (bus1_xpcs_reg_din ),
    .xpcs_reg_dout     (bus1_xpcs_reg_dout),
    .xpcs_reg_busy     (bus1_xpcs_reg_busy),

    .xlpcs_reg_wren    (bus1_xlpcs_reg_wren),
    .xlpcs_reg_rden    (bus1_xlpcs_reg_rden),
    .xlpcs_reg_addr    (bus1_xlpcs_reg_addr),
    .xlpcs_reg_din     (bus1_xlpcs_reg_din ),
    .xlpcs_reg_dout    (bus1_xlpcs_reg_dout),
    .xlpcs_reg_busy    (bus1_xlpcs_reg_busy),

    .mac_reg_wren      (bus1_mac_reg_wren    ),
    .mac_reg_rden      (bus1_mac_reg_rden    ),
    .mac_reg_addr      (bus1_mac_reg_addr    ),
    .mac_reg_din       (bus1_mac_reg_din     ),
    .mac_reg_dout      (bus1_mac_reg_dout    ),
    .mac_reg_busy      (bus1_mac_reg_busy    ),
    .mac_reg_lowp_ena  (1'b0                 ),

    .mac_tx_ts         (bus1_mac_tx_ts       ),
    .mac_frc_in_tx     (bus1_mac_frc_in_tx   ),
    .mac_frc_in_rx     (bus1_mac_frc_in_rx   ),

    //fp_and_sch_top
    .pkt_clk                (pkt_clk                  ),  
    .pkt_rstn               (pkt_rstn                 ),
    .fp_sch_init_done       (fp_sch_init_done0        ),

    //进入bus后有逻辑交叉
    .np_data_in             (npsys_data_in             ),
    .np_addr_in             (npsys_addr_in             ),
    .np_wr_in               (npsys_wr_in_bus1          ),
    .np_rd_in               (npsys_rd_in_bus1          ),
    .np_data_out            (bus1_npsys_data_out       ),
    .bus_np_data_out_vld    (bus1_npsys_data_out_vld   ),
    //.bus_np_addr_ctrl       ({bus1_np_addr_ctrl[53:26],bus1_np_addr_ctrl[23:6]}  ),

    // 总线交叉模块信号处理
    .bus1_table_addr2               (bus1_table_addr             ),
    .bus1_table_ram_addr_convert    (bus1_table_ram_addr_convert ),
    .bus1_table_data2               (bus1_table_data             ),
    .bus1_table_ram_data_convert    (bus1_table_ram_data_convert ),
    .bus1_table_wren2               (bus1_table_wren             ),
    .bus1_table_ram_wr_en_convert   (bus1_table_ram_wr_en_convert),
    .bus2_table_addr2               (bus2_table_addr             ),
    .bus2_table_ram_addr_convert    (bus2_table_ram_addr_convert ),
    .bus2_table_data2               (bus2_table_data             ),
    .bus2_table_ram_data_convert    (bus2_table_ram_data_convert ),
    .bus2_table_wren2               (bus2_table_wren             ),
    .bus2_table_ram_wr_en_convert   (bus2_table_ram_wr_en_convert),
    .bus3_table_addr2               (bus3_table_addr             ),
    .bus3_table_ram_addr_convert    (bus3_table_ram_addr_convert ),
    .bus3_table_data2               (bus3_table_data             ),
    .bus3_table_ram_data_convert    (bus3_table_ram_data_convert ),
    .bus3_table_wren2               (bus3_table_wren             ),
    .bus3_table_ram_wr_en_convert   (bus3_table_ram_wr_en_convert),
    .bus4_table_addr2               (bus4_table_addr             ),
    .bus4_table_ram_addr_convert    (bus4_table_ram_addr_convert ),
    .bus4_table_data2               (bus4_table_data             ),
    .bus4_table_ram_data_convert    (bus4_table_ram_data_convert ),
    .bus4_table_wren2               (bus4_table_wren             ),
    .bus4_table_ram_wr_en_convert   (bus4_table_ram_wr_en_convert),

    .uni_tx_rdy00           (uni_tx_rdy00       ),
    .uni_tx_rdy01           (uni_tx_rdy01       ),
    .uni_tx_rdy02           (uni_tx_rdy02       ),
    .uni_tx_rdy03           (uni_tx_rdy03       ),
    .mul_tx_rdy00           (mul_tx_rdy00       ),
    .mul_tx_rdy01           (mul_tx_rdy01       ),
    .mul_tx_rdy02           (mul_tx_rdy02       ),
    .mul_tx_rdy03           (mul_tx_rdy03       ),

    .emac_data_in           (emac_data_in0      ),   
    .emac_data_wren         (emac_data_wren0    ), 
    .rx_address_dpram       (rx_address_dpram0  ),
    .mac_dest_port_in       (mac_dest_port_in0  ),
    .mul_indicate           (mul_indicate0      ), 

    .pkt_sop_i              (pkt_sop_i_40_0     ),
    .pkt_data_i             (pkt_data_i_40_0    ),
    .pkt_eop_i              (pkt_eop_i_40_0     ),
    .pkt_mod_i              (pkt_mod_i_40_0     ),
    .pkt_dval_i             (pkt_dval_i_40_0    ),

    //mac to np
    .ram_2p_cfg_register    (ram_2p_cfg_out_0 ),
    .ram_dp_cfg_register    (ram_dp_cfg_out_0 ),
    .rf_2p_cfg_register     (rf_2p_cfg_out_0  ),

    `ifdef SIM
        bus_axi_valid_o         (bus0_axi_valid_o   ),
        bus_axi_data_o          (bus0_axi_data_o    ),
        bus_axi_last_o          (bus0_axi_last_o    ),
        bus_axi_keep_o          (bus0_axi_keep_o    ),
        bus_axi_ready_o         (bus0_axi_ready_o   ),

        bus_axi_valid_i         (bus0_axi_valid_i   ),
        bus_axi_data_i          (bus0_axi_data_i    ),
        bus_axi_last_i          (bus0_axi_last_i    ),
        bus_axi_keep_i          (bus0_axi_keep_i    ),
        bus_axi_ready_i         (bus0_axi_ready_i   ),
    `endif

    .emac_rx_ready          (emac_rx_ready0     ),

    // ####################################
    //bus1
    // ####################################
    .vp_1          (vp_1          ),    
    .vpdig_1       (vpdig_1       ),    
    .vph_1         (vph_1         ),     
    .vptx0_1       (vptx0_1       ),     
    .vptx1_1       (vptx1_1       ),     
    .vptx2_1       (vptx2_1       ),     
    .vptx3_1       (vptx3_1       ),     
    .vsscore_0_1   (vsscore_0_1   ),        
    .vsscore_1_1   (vsscore_1_1   ),        
    .vsscore_2_1   (vsscore_2_1   ),        
    .gd_1          (gd_1          ),

    // phy_mac_interface
    .phy_ctrl_register_1                   (bus2_phy_ctrl_register                 ),
    .reset_register_1                      (bus2_reset_register                    ),
    .req_lb_register_1                     (bus2_req_lb_register                   ),
    .ack_register_temp_1                   (bus2_ack_register_temp                 ),
    .mac_pcs_status_register1_1            (bus2_mac_pcs_status_register1          ),
    .mac_pcs_status_register0_temp_1       (bus2_mac_pcs_status_register0_temp     ),
    .mac_pcs_status_register2_temp_1       (bus2_mac_pcs_status_register2_temp     ),

    //jtag signals
    .jtag_tck_1               (jtag_clk              ),
    .jtag_tdi_1               (phy_jtag_tdi_1        ),
    .jtag_tdo_1               (phy_jtag_tdo_1        ),
    .jtag_tdo_en_1            (phy_jtag_tdo_en_1     ),
    .jtag_tms_1               (jtag_tms              ),
    .jtag_trst_n_1            (~jtag_trst            ),

    //clk and clk_en
    .ref_pad_clk_m_1          (ref_pad_clk_m_1        ),
    .ref_pad_clk_p_1          (ref_pad_clk_p_1        ),
    .ref_alt_clk_m_1          (1'b0                   ),//156
    .ref_alt_clk_p_1          (clk156_p               ),

    //Resistor Tune Signals
    .resref_1                 (resref_1               ),

    //serial data signals
    .res_ack_in_1     (res_ack_in_1 ),
    .res_ack_out_1    (res_ack_out_1),
    .res_req_in_1     (res_req_in_1 ),
    .res_req_out_1    (res_req_out_1),

    .rx0_m_1      (rx0_m_1),//in&out
    .rx0_p_1      (rx0_p_1),
    .rx1_m_1      (rx1_m_1),
    .rx1_p_1      (rx1_p_1),
    .rx2_m_1      (rx2_m_1),
    .rx2_p_1      (rx2_p_1),
    .rx3_m_1      (rx3_m_1),
    .rx3_p_1      (rx3_p_1),

    .tx0_m_1      (tx0_m_1),
    .tx0_p_1      (tx0_p_1),
    .tx1_m_1      (tx1_m_1),
    .tx1_p_1      (tx1_p_1),
    .tx2_m_1      (tx2_m_1),
    .tx2_p_1      (tx2_p_1),
    .tx3_m_1      (tx3_m_1),
    .tx3_p_1      (tx3_p_1),

    //mac signals
    .ref_ff_clk_630plus_1       (clk_mac1 ),
    .reg_clk_1                  (pkt_clk  ),

    .xpcs_reg_wren_1     (bus2_xpcs_reg_wren),
    .xpcs_reg_rden_1     (bus2_xpcs_reg_rden),
    .xpcs_reg_addr_1     (bus2_xpcs_reg_addr),
    .xpcs_reg_din_1      (bus2_xpcs_reg_din ),
    .xpcs_reg_dout_1     (bus2_xpcs_reg_dout),
    .xpcs_reg_busy_1     (bus2_xpcs_reg_busy),

    .xlpcs_reg_wren_1    (bus2_xlpcs_reg_wren),
    .xlpcs_reg_rden_1    (bus2_xlpcs_reg_rden),
    .xlpcs_reg_addr_1    (bus2_xlpcs_reg_addr),
    .xlpcs_reg_din_1     (bus2_xlpcs_reg_din ),
    .xlpcs_reg_dout_1    (bus2_xlpcs_reg_dout),
    .xlpcs_reg_busy_1    (bus2_xlpcs_reg_busy),

    .mac_reg_wren_1      (bus2_mac_reg_wren    ),
    .mac_reg_rden_1      (bus2_mac_reg_rden    ),
    .mac_reg_addr_1      (bus2_mac_reg_addr    ),
    .mac_reg_din_1       (bus2_mac_reg_din     ),
    .mac_reg_dout_1      (bus2_mac_reg_dout    ),
    .mac_reg_busy_1      (bus2_mac_reg_busy    ),
    .mac_reg_lowp_ena_1  (1'b0                 ),
    .mac_tx_ts_1         (bus2_mac_tx_ts       ),
    .mac_frc_in_tx_1     (bus2_mac_frc_in_tx   ),
    .mac_frc_in_rx_1     (bus2_mac_frc_in_rx   ),

    //fp_and_sch_top
    .pkt_clk_1                (pkt_clk                  ),  
    .pkt_rstn_1               (pkt_rstn                 ),
    .fp_sch_init_done_1       (fp_sch_init_done1        ),

    //进入bus后有逻辑交叉
    .np_data_in_1             (npsys_data_in             ),
    .np_addr_in_1             (npsys_addr_in             ),
    .np_wr_in_1               (npsys_wr_in_bus2            ),
    .np_rd_in_1               (npsys_rd_in_bus2            ),
    .np_data_out_1            (bus2_npsys_data_out       ),
    .bus_np_data_out_vld_1    (bus2_npsys_data_out_vld   ),
    //.bus_np_addr_ctrl_1          (bus2_np_addr_ctrl[51:6]  ),

    // 总线交叉模块信号处理
    // .bus1_table_addr2_1               (bus2_table_addr             ),
    // .bus1_table_ram_addr_convert_1    (bus2_table_ram_addr_convert ),
    // .bus1_table_data2_1               (bus2_table_data             ),
    // .bus1_table_ram_data_convert_1    (bus2_table_ram_data_convert ),
    // .bus1_table_wren2_1               (bus2_table_wren             ),
    // .bus1_table_ram_wr_en_convert_1   (bus2_table_ram_wr_en_convert),
    // //.bus2_table_addr2_1               (bus1_table_addr             ),
    // //.bus2_table_ram_addr_convert_1    (bus1_table_ram_addr_convert ),
    // //.bus2_table_data2_1               (bus1_table_data             ),
    // //.bus2_table_ram_data_convert_1    (bus1_table_ram_data_convert ),
    // //.bus2_table_wren2_1               (bus1_table_wren             ),
    // //.bus2_table_ram_wr_en_convert_1   (bus1_table_ram_wr_en_convert),
    // .bus3_table_addr2_1               (bus3_table_addr             ),
    // .bus3_table_ram_addr_convert_1    (bus3_table_ram_addr_convert ),
    // .bus3_table_data2_1               (bus3_table_data             ),
    // .bus3_table_ram_data_convert_1    (bus3_table_ram_data_convert ),
    // .bus3_table_wren2_1               (bus3_table_wren             ),
    // .bus3_table_ram_wr_en_convert_1   (bus3_table_ram_wr_en_convert),
    // .bus4_table_addr2_1               (bus4_table_addr             ),
    // .bus4_table_ram_addr_convert_1    (bus4_table_ram_addr_convert ),
    // .bus4_table_data2_1               (bus4_table_data             ),
    // .bus4_table_ram_data_convert_1    (bus4_table_ram_data_convert ),
    // .bus4_table_wren2_1               (bus4_table_wren             ),
    // .bus4_table_ram_wr_en_convert_1   (bus4_table_ram_wr_en_convert),

    .uni_tx_rdy00_1           (uni_tx_rdy10       ),
    .uni_tx_rdy01_1           (uni_tx_rdy11       ),
    .uni_tx_rdy02_1           (uni_tx_rdy12       ),
    .uni_tx_rdy03_1           (uni_tx_rdy13       ),
    .mul_tx_rdy00_1           (mul_tx_rdy10       ),
    .mul_tx_rdy01_1           (mul_tx_rdy11       ),
    .mul_tx_rdy02_1           (mul_tx_rdy12       ),
    .mul_tx_rdy03_1           (mul_tx_rdy13       ),

    .emac_data_in_1            (emac_data_in1      ),   
    .emac_data_wren_1          (emac_data_wren1    ), 
    .rx_address_dpram_1        (rx_address_dpram1  ),
    .mac_dest_port_in_1        (mac_dest_port_in1  ),
    .mul_indicate_1            (mul_indicate1      ), 

    .pkt_sop_i_1              (pkt_sop_i_40_1     ),
    .pkt_data_i_1             (pkt_data_i_40_1    ),
    .pkt_eop_i_1              (pkt_eop_i_40_1     ),
    .pkt_mod_i_1              (pkt_mod_i_40_1     ),
    .pkt_dval_i_1             (pkt_dval_i_40_1    ),

    `ifdef SIM
        bus_axi_valid_o_1         (bus1_axi_valid_o   ),
        bus_axi_data_o_1          (bus1_axi_data_o    ),
        bus_axi_last_o_1          (bus1_axi_last_o    ),
        bus_axi_keep_o_1          (bus1_axi_keep_o    ),
        bus_axi_ready_o_1         (bus1_axi_ready_o   ),

        bus_axi_valid_i_1         (bus1_axi_valid_i   ),
        bus_axi_data_i_1          (bus1_axi_data_i    ),
        bus_axi_last_i_1          (bus1_axi_last_i    ),
        bus_axi_keep_i_1          (bus1_axi_keep_i    ),
        bus_axi_ready_i_1         (bus1_axi_ready_i   ),
    `endif

    .emac_rx_ready_1          (emac_rx_ready1     ),

    // DMA interface signals
     // AHB input
    .HCLK                     (ahbclk),
    .HRESETn                  (ahbresetn),
    .HSEL                     (np_hselx_ahbm_0),
    .HREADY                   (np_hready_ahbm_0),
    .HTRANS                   (np_htrans_ahbm_0),
    .HSIZE                    (np_hsize_ahbm_0),
    .HWRITE                   (np_hwrite_ahbm_0),
    .HADDR                    (np_haddr_ahbm_0),
    .HWDATA                   (np_hwdata_ahbm_0),
     // AHB output
    .HREADYOUT                (hreadyout_ahbm_0),
    .HRESP                    (hresp_ahbm_0),
    .HRDATA                   (hrdata_np_dma_0),
    .np_dma_irq_o             (np_dma_m0_irq_o),
    // AXI master
    .m_axi_aclk_i             (m_axi_aclk_i),
    .m_axi_aresetn_i          (m_axi_aresetn_i),
    .m_axi_awid_o             (m_axi_m0_awid_o),
    .m_axi_awaddr_o           (m_axi_m0_awaddr_o),
    .m_axi_awlen_o            (m_axi_m0_awlen_o),
    .m_axi_awsize_o           (m_axi_m0_awsize_o),
    .m_axi_awburst_o          (m_axi_m0_awburst_o),
    .m_axi_awlock_o           (m_axi_m0_awlock_o),
    .m_axi_awcache_o          (m_axi_m0_awcache_o),
    .m_axi_awprot_o           (m_axi_m0_awprot_o),
    .m_axi_awqos_o            (m_axi_m0_awqos_o),
    .m_axi_awuser_o           (m_axi_m0_awuser_o),
    .m_axi_awvalid_o          (m_axi_m0_awvalid_o),
    .m_axi_awready_i          (m_axi_m0_awready_i),
    .m_axi_wdata_o            (m_axi_m0_wdata_o),
    .m_axi_wstrb_o            (m_axi_m0_wstrb_o),
    .m_axi_wlast_o            (m_axi_m0_wlast_o),
    .m_axi_wuser_o            (m_axi_m0_wuser_o),
    .m_axi_wvalid_o           (m_axi_m0_wvalid_o),
    .m_axi_wready_i           (m_axi_m0_wready_i),
    .m_axi_bid_i              (m_axi_m0_bid_i),
    .m_axi_bresp_i            (m_axi_m0_bresp_i),
    .m_axi_buser_i            (m_axi_m0_buser_i),
    .m_axi_bvalid_i           (m_axi_m0_bvalid_i),
    .m_axi_bready_o           (m_axi_m0_bready_o),
    .m_axi_arid_o             (m_axi_m0_arid_o),
    .m_axi_araddr_o           (m_axi_m0_araddr_o),
    .m_axi_arlen_o            (m_axi_m0_arlen_o),
    .m_axi_arsize_o           (m_axi_m0_arsize_o),
    .m_axi_arburst_o          (m_axi_m0_arburst_o),
    .m_axi_arlock_o           (m_axi_m0_arlock_o),
    .m_axi_arcache_o          (m_axi_m0_arcache_o),
    .m_axi_arprot_o           (m_axi_m0_arprot_o),
    .m_axi_arqos_o            (m_axi_m0_arqos_o),
    .m_axi_aruser_o           (m_axi_m0_aruser_o),
    .m_axi_arvalid_o          (m_axi_m0_arvalid_o),
    .m_axi_arready_i          (m_axi_m0_arready_i),
    .m_axi_rid_i              (m_axi_m0_rid_i),
    .m_axi_rdata_i            (m_axi_m0_rdata_i),
    .m_axi_rresp_i            (m_axi_m0_rresp_i),
    .m_axi_rlast_i            (m_axi_m0_rlast_i),
    .m_axi_ruser_i            (m_axi_m0_ruser_i),
    .m_axi_rvalid_i           (m_axi_m0_rvalid_i),
    .m_axi_rready_o           (m_axi_m0_rready_o),

    .dma_channel_sel          (dma_channel_sel0),

    // DFT port
    .testmode                 ( testmode       ),
    .se                       ( se             ),
    .phy_scan_clk             ( phy_scan_clk   )
  );

// #########################################################################################
//bus3 & bus4
// #########################################################################################
  // double_bus #(
  //   .frame_mac_dst_bus0  (48'h1000_0000_0004   ),
  //   .frame_mac_src_bus0  (48'h1000_0000_0003   ),
  //   .frame_length_bus0   (16'h88b6             ),
  //   .CLUSTER_ID0         (2'b10),

  //   .frame_mac_dst_bus1  (48'h1000_0000_0003   ),
  //   .frame_mac_src_bus1  (48'h1000_0000_0004   ),
  //   .frame_length_bus1   (16'h88b6             ),
  //   .CLUSTER_ID1         (2'b11),

  //   .NP_DMA_BASE_ADDR         (NP_DMA1_BASE_ADDR),
  //   .MAC_USER_WIDTH           (MAC_USER_WIDTH),
  //   .AXI_BURST_LEN            (AXI_BURST_LEN),
  //   .AXI_ID_WIDTH             (AXI_ID_WIDTH),
  //   .AXI_ADDR_WIDTH           (AXI_ADDR_WIDTH),
  //   .AXI_DATA_WIDTH           (AXI_DATA_WIDTH),
  //   .AXI_LIB_WIDTH            (AXI_LIB_WIDTH),
  //   .AXI_AWUSER_WIDTH         (AXI_AWUSER_WIDTH),
  //   .AXI_ARUSER_WIDTH         (AXI_ARUSER_WIDTH),
  //   .AXI_WUSER_WIDTH          (AXI_WUSER_WIDTH),
  //   .AXI_RUSER_WIDTH          (AXI_RUSER_WIDTH),
  //   .AXI_BUSER_WIDTH          (AXI_BUSER_WIDTH)
  //   )
  double_bus
    u_double_bus_3_4(
    // ####################################
    //bus0
    // ####################################
    //param
    .frame_mac_dst_bus0(48'h1000_0000_0004),
    .frame_mac_src_bus0(48'h1000_0000_0003),
    .cluster_id_bus0(2'b10),
    .frame_mac_dst_bus1(48'h1000_0000_0003),
    .frame_mac_src_bus1(48'h1000_0000_0004),
    .cluster_id_bus1(2'b11),
    .dma_addr(NP_DMA1_BASE_ADDR),

    //phy信号
    .vp          (vp_2          ),    
    .vpdig       (vpdig_2       ),    
    .vph         (vph_2         ),     
    .vptx0       (vptx0_2       ),     
    .vptx1       (vptx1_2       ),     
    .vptx2       (vptx2_2       ),     
    .vptx3       (vptx3_2       ),     
    .vsscore_0   (vsscore_0_2   ),        
    .vsscore_1   (vsscore_1_2   ),        
    .vsscore_2   (vsscore_2_2   ),        
    .gd          (gd_2          ),

    // phy_mac_interface
    .phy_ctrl_register                   (bus3_phy_ctrl_register                 ),
    .reset_register                      (bus3_reset_register                    ),
    .req_lb_register                     (bus3_req_lb_register                   ),
    .ack_register_temp                   (bus3_ack_register_temp                 ),
    .mac_pcs_status_register1            (bus3_mac_pcs_status_register1          ),
    .mac_pcs_status_register0_temp       (bus3_mac_pcs_status_register0_temp     ),
    .mac_pcs_status_register2_temp       (bus3_mac_pcs_status_register2_temp     ),

    //jtag signals
    .jtag_tck               (jtag_clk              ),
    .jtag_tdi               (phy_jtag_tdi_2        ),
    .jtag_tdo               (phy_jtag_tdo_2        ),
    .jtag_tdo_en            (phy_jtag_tdo_en_2     ),
    .jtag_tms               (jtag_tms              ),
    .jtag_trst_n            (~jtag_trst            ),

    //clk and clk_en
    .ref_pad_clk_m          (ref_pad_clk_m_2        ),
    .ref_pad_clk_p          (ref_pad_clk_p_2        ),
    .ref_alt_clk_m          (1'b0                   ),//156
    .ref_alt_clk_p          (clk156_p               ),

    //Resistor Tune Signals
    .resref                 (resref_2               ),

    //serial data signals
    .res_ack_in     (res_ack_in_2 ),
    .res_ack_out    (res_ack_out_2),
    .res_req_in     (res_req_in_2 ),
    .res_req_out    (res_req_out_2),

    .rx0_m      (rx0_m_2),//in&out
    .rx0_p      (rx0_p_2),
    .rx1_m      (rx1_m_2),
    .rx1_p      (rx1_p_2),
    .rx2_m      (rx2_m_2),
    .rx2_p      (rx2_p_2),
    .rx3_m      (rx3_m_2),
    .rx3_p      (rx3_p_2),

    .tx0_m      (tx0_m_2),
    .tx0_p      (tx0_p_2),
    .tx1_m      (tx1_m_2),
    .tx1_p      (tx1_p_2),
    .tx2_m      (tx2_m_2),
    .tx2_p      (tx2_p_2),
    .tx3_m      (tx3_m_2),
    .tx3_p      (tx3_p_2),

    //mac signals
    .ref_ff_clk_630plus       (clk_mac1 ),
    .reg_clk                  (pkt_clk ),

    .xpcs_reg_wren     (bus3_xpcs_reg_wren),
    .xpcs_reg_rden     (bus3_xpcs_reg_rden),
    .xpcs_reg_addr     (bus3_xpcs_reg_addr),
    .xpcs_reg_din      (bus3_xpcs_reg_din ),
    .xpcs_reg_dout     (bus3_xpcs_reg_dout),
    .xpcs_reg_busy     (bus3_xpcs_reg_busy),

    .xlpcs_reg_wren    (bus3_xlpcs_reg_wren),
    .xlpcs_reg_rden    (bus3_xlpcs_reg_rden),
    .xlpcs_reg_addr    (bus3_xlpcs_reg_addr),
    .xlpcs_reg_din     (bus3_xlpcs_reg_din ),
    .xlpcs_reg_dout    (bus3_xlpcs_reg_dout),
    .xlpcs_reg_busy    (bus3_xlpcs_reg_busy),

    .mac_reg_wren      (bus3_mac_reg_wren    ),
    .mac_reg_rden      (bus3_mac_reg_rden    ),
    .mac_reg_addr      (bus3_mac_reg_addr    ),
    .mac_reg_din       (bus3_mac_reg_din     ),
    .mac_reg_dout      (bus3_mac_reg_dout    ),
    .mac_reg_busy      (bus3_mac_reg_busy    ),
    .mac_reg_lowp_ena  (1'b0                 ),
    .mac_tx_ts         (bus3_mac_tx_ts       ),
    .mac_frc_in_tx     (bus3_mac_frc_in_tx   ),
    .mac_frc_in_rx     (bus3_mac_frc_in_rx   ),

    //fp_and_sch_top
    .pkt_clk                (pkt_clk                  ),  
    .pkt_rstn               (pkt_rstn                 ),
    .fp_sch_init_done       (fp_sch_init_done2        ),

    //进入bus后有逻辑交叉
    .np_data_in             (npsys_data_in             ),
    .np_addr_in             (npsys_addr_in             ),
    .np_wr_in               (npsys_wr_in_bus3              ),
    .np_rd_in               (npsys_rd_in_bus3              ),
    .np_data_out            (bus3_npsys_data_out       ),
    .bus_np_data_out_vld    (bus3_npsys_data_out_vld   ),
    // .bus_np_addr_ctrl       (bus3_np_addr_ctrl[51:6]   ),

    // 总线交叉模块信号处理
    .bus1_table_addr2               (bus3_table_addr             ),
    .bus1_table_ram_addr_convert    (bus3_table_ram_addr_convert ),
    .bus1_table_data2               (bus3_table_data             ),
    .bus1_table_ram_data_convert    (bus3_table_ram_data_convert ),
    .bus1_table_wren2               (bus3_table_wren             ),
    .bus1_table_ram_wr_en_convert   (bus3_table_ram_wr_en_convert),
    .bus2_table_addr2               (bus4_table_addr             ),
    .bus2_table_ram_addr_convert    (bus4_table_ram_addr_convert ),
    .bus2_table_data2               (bus4_table_data             ),
    .bus2_table_ram_data_convert    (bus4_table_ram_data_convert ),
    .bus2_table_wren2               (bus4_table_wren             ),
    .bus2_table_ram_wr_en_convert   (bus4_table_ram_wr_en_convert),
    .bus3_table_addr2               (bus1_table_addr             ),
    .bus3_table_ram_addr_convert    (bus1_table_ram_addr_convert ),
    .bus3_table_data2               (bus1_table_data             ),
    .bus3_table_ram_data_convert    (bus1_table_ram_data_convert ),
    .bus3_table_wren2               (bus1_table_wren             ),
    .bus3_table_ram_wr_en_convert   (bus1_table_ram_wr_en_convert),
    .bus4_table_addr2               (bus2_table_addr             ),
    .bus4_table_ram_addr_convert    (bus2_table_ram_addr_convert ),
    .bus4_table_data2               (bus2_table_data             ),
    .bus4_table_ram_data_convert    (bus2_table_ram_data_convert ),
    .bus4_table_wren2               (bus2_table_wren             ),
    .bus4_table_ram_wr_en_convert   (bus2_table_ram_wr_en_convert),

    .uni_tx_rdy00           (uni_tx_rdy20       ),
    .uni_tx_rdy01           (uni_tx_rdy21       ),
    .uni_tx_rdy02           (uni_tx_rdy22       ),
    .uni_tx_rdy03           (uni_tx_rdy23       ),
    .mul_tx_rdy00           (mul_tx_rdy20       ),
    .mul_tx_rdy01           (mul_tx_rdy21       ),
    .mul_tx_rdy02           (mul_tx_rdy22       ),
    .mul_tx_rdy03           (mul_tx_rdy23       ),

    .emac_data_in           (emac_data_in2      ),   
    .emac_data_wren         (emac_data_wren2    ), 
    .rx_address_dpram       (rx_address_dpram2  ),
    .mac_dest_port_in       (mac_dest_port_in2  ),
    .mul_indicate           (mul_indicate2      ), 

    .pkt_sop_i              (pkt_sop_i_10_0     ),
    .pkt_data_i             (pkt_data_i_10_0    ),
    .pkt_eop_i              (pkt_eop_i_10_0     ),
    .pkt_mod_i              (pkt_mod_i_10_0     ),
    .pkt_dval_i             (pkt_dval_i_10_0    ),

    //mac to np
    .ram_2p_cfg_register    (ram_2p_cfg_out_1 ),
    .ram_dp_cfg_register    (ram_dp_cfg_out_1 ),
    .rf_2p_cfg_register     (rf_2p_cfg_out_1  ),

    `ifdef SIM
        bus_axi_valid_o         (bus2_axi_valid_o   ),
        bus_axi_data_o          (bus2_axi_data_o    ),
        bus_axi_last_o          (bus2_axi_last_o    ),
        bus_axi_keep_o          (bus2_axi_keep_o    ),
        bus_axi_ready_o         (bus2_axi_ready_o   ),

        bus_axi_valid_i         (bus2_axi_valid_i   ),
        bus_axi_data_i          (bus2_axi_data_i    ),
        bus_axi_last_i          (bus2_axi_last_i    ),
        bus_axi_keep_i          (bus2_axi_keep_i    ),
        bus_axi_ready_i         (bus2_axi_ready_i   ),
    `endif

    .emac_rx_ready          (emac_rx_ready2     ),

    // ####################################
    //bus1
    // ####################################
    //phy信号
    .vp_1          (vp_3          ),    
    .vpdig_1       (vpdig_3       ),    
    .vph_1         (vph_3         ),     
    .vptx0_1       (vptx0_3       ),     
    .vptx1_1       (vptx1_3       ),     
    .vptx2_1       (vptx2_3       ),     
    .vptx3_1       (vptx3_3       ),     
    .vsscore_0_1   (vsscore_0_3   ),        
    .vsscore_1_1   (vsscore_1_3   ),        
    .vsscore_2_1   (vsscore_2_3   ),        
    .gd_1          (gd_3          ),

    // phy_mac_interface
    .phy_ctrl_register_1                   (bus4_phy_ctrl_register                 ),
    .reset_register_1                      (bus4_reset_register                    ),
    .req_lb_register_1                     (bus4_req_lb_register                   ),
    .ack_register_temp_1                   (bus4_ack_register_temp                 ),
    .mac_pcs_status_register1_1            (bus4_mac_pcs_status_register1          ),
    .mac_pcs_status_register0_temp_1       (bus4_mac_pcs_status_register0_temp     ),
    .mac_pcs_status_register2_temp_1       (bus4_mac_pcs_status_register2_temp     ),

    //jtag signals
    .jtag_tck_1               (jtag_clk              ),
    .jtag_tdi_1               (phy_jtag_tdi_3        ),
    .jtag_tdo_1               (phy_jtag_tdo_3        ),
    .jtag_tdo_en_1            (phy_jtag_tdo_en_3     ),
    .jtag_tms_1               (jtag_tms              ),
    .jtag_trst_n_1            (~jtag_trst            ),

    //clk and clk_en
    .ref_pad_clk_m_1          (ref_pad_clk_m_3        ),
    .ref_pad_clk_p_1          (ref_pad_clk_p_3        ),
    .ref_alt_clk_m_1          (1'b0                   ),//156
    .ref_alt_clk_p_1          (clk156_p               ),

    //Resistor Tune Signals
    .resref_1                 (resref_3               ),

    //serial data signals
    .res_ack_in_1     (res_ack_in_3 ),
    .res_ack_out_1    (res_ack_out_3),
    .res_req_in_1     (res_req_in_3 ),
    .res_req_out_1    (res_req_out_3),

    .rx0_m_1     (rx0_m_3),//in&out
    .rx0_p_1     (rx0_p_3),
    .rx1_m_1     (rx1_m_3),
    .rx1_p_1     (rx1_p_3),
    .rx2_m_1     (rx2_m_3),
    .rx2_p_1     (rx2_p_3),
    .rx3_m_1     (rx3_m_3),
    .rx3_p_1     (rx3_p_3),

    .tx0_m_1     (tx0_m_3),
    .tx0_p_1     (tx0_p_3),
    .tx1_m_1     (tx1_m_3),
    .tx1_p_1     (tx1_p_3),
    .tx2_m_1     (tx2_m_3),
    .tx2_p_1     (tx2_p_3),
    .tx3_m_1     (tx3_m_3),
    .tx3_p_1     (tx3_p_3),

    //mac signals
    .ref_ff_clk_630plus_1       (clk_mac1 ),
    .reg_clk_1                  (pkt_clk  ),

    .xpcs_reg_wren_1     (bus4_xpcs_reg_wren),
    .xpcs_reg_rden_1     (bus4_xpcs_reg_rden),
    .xpcs_reg_addr_1     (bus4_xpcs_reg_addr),
    .xpcs_reg_din_1      (bus4_xpcs_reg_din ),
    .xpcs_reg_dout_1     (bus4_xpcs_reg_dout),
    .xpcs_reg_busy_1     (bus4_xpcs_reg_busy),

    .xlpcs_reg_wren_1    (bus4_xlpcs_reg_wren),
    .xlpcs_reg_rden_1    (bus4_xlpcs_reg_rden),
    .xlpcs_reg_addr_1    (bus4_xlpcs_reg_addr),
    .xlpcs_reg_din_1     (bus4_xlpcs_reg_din ),
    .xlpcs_reg_dout_1    (bus4_xlpcs_reg_dout),
    .xlpcs_reg_busy_1    (bus4_xlpcs_reg_busy),

    .mac_reg_wren_1      (bus4_mac_reg_wren    ),
    .mac_reg_rden_1      (bus4_mac_reg_rden    ),
    .mac_reg_addr_1      (bus4_mac_reg_addr    ),
    .mac_reg_din_1       (bus4_mac_reg_din     ),
    .mac_reg_dout_1      (bus4_mac_reg_dout    ),
    .mac_reg_busy_1      (bus4_mac_reg_busy    ),
    .mac_reg_lowp_ena_1  (1'b0                 ),
    .mac_tx_ts_1         (bus4_mac_tx_ts       ),
    .mac_frc_in_tx_1     (bus4_mac_frc_in_tx   ),
    .mac_frc_in_rx_1     (bus4_mac_frc_in_rx   ),

    //fp_and_sch_top
    .pkt_clk_1                (pkt_clk                  ),  
    .pkt_rstn_1               (pkt_rstn                 ),
    .fp_sch_init_done_1       (fp_sch_init_done3        ),

    //进入bus后有逻辑交叉
    .np_data_in_1             (npsys_data_in             ),
    .np_addr_in_1             (npsys_addr_in             ),
    .np_wr_in_1               (npsys_wr_in_bus4          ),
    .np_rd_in_1               (npsys_rd_in_bus4              ),
    .np_data_out_1            (bus4_npsys_data_out       ),
    .bus_np_data_out_vld_1    (bus4_npsys_data_out_vld   ),
    //.bus_np_addr_ctrl_1       (bus4_np_addr_ctrl[51:6]   ),

    // 总线交叉模块信号处理
    // .bus1_table_addr2_1               (bus4_table_addr             ),
    // .bus1_table_ram_addr_convert_1    (bus4_table_ram_addr_convert ),
    // .bus1_table_data2_1               (bus4_table_data             ),
    // .bus1_table_ram_data_convert_1    (bus4_table_ram_data_convert ),
    // .bus1_table_wren2_1               (bus4_table_wren             ),
    // .bus1_table_ram_wr_en_convert_1   (bus4_table_ram_wr_en_convert),
    // //.bus2_table_addr2_1               (bus3_table_addr             ),
    // //.bus2_table_ram_addr_convert_1    (bus3_table_ram_addr_convert ),
    // //.bus2_table_data2_1               (bus3_table_data             ),
    // //.bus2_table_ram_data_convert_1    (bus3_table_ram_data_convert ),
    // //.bus2_table_wren2_1               (bus3_table_wren             ),
    // //.bus2_table_ram_wr_en_convert_1   (bus3_table_ram_wr_en_convert),
    // .bus3_table_addr2_1               (bus1_table_addr             ),
    // .bus3_table_ram_addr_convert_1    (bus1_table_ram_addr_convert ),
    // .bus3_table_data2_1               (bus1_table_data             ),
    // .bus3_table_ram_data_convert_1    (bus1_table_ram_data_convert ),
    // .bus3_table_wren2_1               (bus1_table_wren             ),
    // .bus3_table_ram_wr_en_convert_1   (bus1_table_ram_wr_en_convert),
    // .bus4_table_addr2_1               (bus2_table_addr             ),
    // .bus4_table_ram_addr_convert_1    (bus2_table_ram_addr_convert ),
    // .bus4_table_data2_1               (bus2_table_data             ),
    // .bus4_table_ram_data_convert_1    (bus2_table_ram_data_convert ),
    // .bus4_table_wren2_1               (bus2_table_wren             ),
    // .bus4_table_ram_wr_en_convert_1   (bus2_table_ram_wr_en_convert),

    .uni_tx_rdy00_1           (uni_tx_rdy30       ),
    .uni_tx_rdy01_1           (uni_tx_rdy31       ),
    .uni_tx_rdy02_1           (uni_tx_rdy32       ),
    .uni_tx_rdy03_1           (uni_tx_rdy33       ),
    .mul_tx_rdy00_1           (mul_tx_rdy30       ),
    .mul_tx_rdy01_1           (mul_tx_rdy31       ),
    .mul_tx_rdy02_1           (mul_tx_rdy32       ),
    .mul_tx_rdy03_1           (mul_tx_rdy33       ),

    .emac_data_in_1            (emac_data_in3      ),   
    .emac_data_wren_1          (emac_data_wren3    ), 
    .rx_address_dpram_1        (rx_address_dpram3  ),
    .mac_dest_port_in_1        (mac_dest_port_in3  ),
    .mul_indicate_1            (mul_indicate3      ), 

    .pkt_sop_i_1              (pkt_sop_i_10_1     ),
    .pkt_data_i_1             (pkt_data_i_10_1    ),
    .pkt_eop_i_1              (pkt_eop_i_10_1     ),
    .pkt_mod_i_1              (pkt_mod_i_10_1     ),
    .pkt_dval_i_1             (pkt_dval_i_10_1    ),

    `ifdef SIM
        bus_axi_valid_o_1         (bus3_axi_valid_o   ),
        bus_axi_data_o_1          (bus3_axi_data_o    ),
        bus_axi_last_o_1          (bus3_axi_last_o    ),
        bus_axi_keep_o_1          (bus3_axi_keep_o    ),
        bus_axi_ready_o_1         (bus3_axi_ready_o   ),

        bus_axi_valid_i_1         (bus3_axi_valid_i   ),
        bus_axi_data_i_1          (bus3_axi_data_i    ),
        bus_axi_last_i_1          (bus3_axi_last_i    ),
        bus_axi_keep_i_1          (bus3_axi_keep_i    ),
        bus_axi_ready_i_1         (bus3_axi_ready_i   ),
    `endif

    .emac_rx_ready_1          (emac_rx_ready3     ),

    // DMA interface signals
     // AHB input
    .HCLK                     (ahbclk),
    .HRESETn                  (ahbresetn),
    .HSEL                     (np_hselx_ahbm_1),
    .HREADY                   (np_hready_ahbm_1),
    .HTRANS                   (np_htrans_ahbm_1),
    .HSIZE                    (np_hsize_ahbm_1),
    .HWRITE                   (np_hwrite_ahbm_1),
    .HADDR                    (np_haddr_ahbm_1),
    .HWDATA                   (np_hwdata_ahbm_1),
     // AHB output
    .HREADYOUT                (hreadyout_ahbm_1),
    .HRESP                    (hresp_ahbm_1),
    .HRDATA                   (hrdata_np_dma_1),
    .np_dma_irq_o             (np_dma_m1_irq_o),
    // AXI master
    .m_axi_aclk_i             (m_axi_aclk_i),
    .m_axi_aresetn_i          (m_axi_aresetn_i),
    .m_axi_awid_o             (m_axi_m1_awid_o),
    .m_axi_awaddr_o           (m_axi_m1_awaddr_o),
    .m_axi_awlen_o            (m_axi_m1_awlen_o),
    .m_axi_awsize_o           (m_axi_m1_awsize_o),
    .m_axi_awburst_o          (m_axi_m1_awburst_o),
    .m_axi_awlock_o           (m_axi_m1_awlock_o),
    .m_axi_awcache_o          (m_axi_m1_awcache_o),
    .m_axi_awprot_o           (m_axi_m1_awprot_o),
    .m_axi_awqos_o            (m_axi_m1_awqos_o),
    .m_axi_awuser_o           (m_axi_m1_awuser_o),
    .m_axi_awvalid_o          (m_axi_m1_awvalid_o),
    .m_axi_awready_i          (m_axi_m1_awready_i),
    .m_axi_wdata_o            (m_axi_m1_wdata_o),
    .m_axi_wstrb_o            (m_axi_m1_wstrb_o),
    .m_axi_wlast_o            (m_axi_m1_wlast_o),
    .m_axi_wuser_o            (m_axi_m1_wuser_o),
    .m_axi_wvalid_o           (m_axi_m1_wvalid_o),
    .m_axi_wready_i           (m_axi_m1_wready_i),
    .m_axi_bid_i              (m_axi_m1_bid_i),
    .m_axi_bresp_i            (m_axi_m1_bresp_i),
    .m_axi_buser_i            (m_axi_m1_buser_i),
    .m_axi_bvalid_i           (m_axi_m1_bvalid_i),
    .m_axi_bready_o           (m_axi_m1_bready_o),
    .m_axi_arid_o             (m_axi_m1_arid_o),
    .m_axi_araddr_o           (m_axi_m1_araddr_o),
    .m_axi_arlen_o            (m_axi_m1_arlen_o),
    .m_axi_arsize_o           (m_axi_m1_arsize_o),
    .m_axi_arburst_o          (m_axi_m1_arburst_o),
    .m_axi_arlock_o           (m_axi_m1_arlock_o),
    .m_axi_arcache_o          (m_axi_m1_arcache_o),
    .m_axi_arprot_o           (m_axi_m1_arprot_o),
    .m_axi_arqos_o            (m_axi_m1_arqos_o),
    .m_axi_aruser_o           (m_axi_m1_aruser_o),
    .m_axi_arvalid_o          (m_axi_m1_arvalid_o),
    .m_axi_arready_i          (m_axi_m1_arready_i),
    .m_axi_rid_i              (m_axi_m1_rid_i),
    .m_axi_rdata_i            (m_axi_m1_rdata_i),
    .m_axi_rresp_i            (m_axi_m1_rresp_i),
    .m_axi_rlast_i            (m_axi_m1_rlast_i),
    .m_axi_ruser_i            (m_axi_m1_ruser_i),
    .m_axi_rvalid_i           (m_axi_m1_rvalid_i),
    .m_axi_rready_o           (m_axi_m1_rready_o),

    .dma_channel_sel          (dma_channel_sel1),

    // DFT port
    .testmode                 ( testmode       ),
    .se                       ( se             ),
    .phy_scan_clk             ( phy_scan_clk   )
  );

endmodule
